Data processing apparatus comprising an array controller for separating an instruction stream processing instructions and data transfer instructions

• US 8,171,263 B2
• Filed: 06/29/2007
• Issued: 05/01/2012
• Est. Priority Date: 04/09/1999
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Stuttard, Dave, Williams, Dave, O'Dea, Eamon, Faulds, Gordon, Rhoades, John, Cameron, Ken, Atkin, Phil, Winser, Paul, David, Russell, McConnell, Ray, Day, Tim, Greer, Trey
• Primary Examiner(s): LI, AIMEE J
• Application Number:
  US11/772,037
• Publication Number:
  US 20080034185A1
• Time in Patent Office: 1,768 Days
• Field of Search: 712/14, 712/22, 712/216, 712/217, 712/225
• US Class Current: 712/216
• CPC Class Codes: G06F 15/00 Digital computers in general details G06F1/00 – G06F13/00; Data processing equipment in general
• CPC Class Codes: G06F 15/8007 single instruction multiple data [SIMD] multiprocessors
• CPC Class Codes: G06F 15/8015 One dimensional arrays, e.g. rings, linear arrays, buses
• CPC Class Codes: G06F 9/3001 Arithmetic instructions
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3838 Dependency mechanisms, e.g. register scoreboarding
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/3887 controlled by a single instruction for multiple data lanes [SIMD]
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining

Abstract

A parallel data processing apparatus using a SIMD array of processing elements is disclosed. The apparatus makes use of a register in order to control issuance of instructions to the processing elements in the array.

Claims

1. A data processing apparatus comprising:

a SIMD (single instruction multiple data) array of processing elements operable to process data items and each comprising a processor unit, which includes a plurality of registers for storing data therein, and an internal memory unit; and

an array controller which is connected to receive instructions, and is operable to control the operation of the SIMD array in accordance with the received instructions, wherein the array controller comprises;

an instruction launcher for separating received instructions into—

data processing instructions and data transfer instructions and for locking registers associated with the received instructions, wherein the instruction launcher is configured to access an instruction table containing microcode information to determine an instruction type for an instruction and to determine which registers are accessed by the instruction;

a processing element instruction sequencer for receiving data processing instructions from the instruction launcher, for indexing a microcode store containing microcodes readable by the processing elements of said SIMD array of processing elements, and for transferring the microcode to the processing elements of said SIMD array of processing elements;

a data transfer controller for receiving data transfer instructions from the instruction launcher and for controlling data transfer to and from the respective internal memory units of the processing elements; and

a register use monitor unit operable to record which of the processor unit registers are in use by an instruction.

2. A data processing apparatus as claimed in claim 1, wherein the register use monitor means is operable to prevent operation of a further instruction that requires use of registers that are already in use by an instruction.

3. A data processing apparatus as claimed in claim 1, wherein the processing elements are operably divided into a plurality of processing blocks for processing respective groups of data items.

4. An apparatus as claimed in claim 1, provided on a single integrated circuit.

5. A graphical data processing system comprising a host general data processing apparatus and a data processing apparatus as claimed in claim 1, for processing graphical data.