Reporting flash memory operating voltages

• US 8,171,318 B2
• Filed: 03/02/2010
• Issued: 05/01/2012
• Est. Priority Date: 01/25/2006
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Cornwell, Michael J., Dudte, Christopher P., Fisher, Joseph R. Jr.
• Primary Examiner(s): Lee, Thomas
• Assistant Examiner(s): Abbaszadeh, Jaweed A
• Application Number:
  US12/716,153
• Publication Number:
  US 20100162012A1
• Time in Patent Office: 791 Days
• Field of Search: 713/300, 713/320, 365/189.15, 365/226, 307/31, 711/100, 711/102
• US Class Current: 713/320
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C

Abstract

Apparatus and associated systems, methods and computer program products relate to using information stored in a flash memory to adjust the operating voltage supplied to the flash memory. The voltage information indicates a minimum operating voltage at which to operate the flash memory device. In general, operating a flash memory device near a minimal operating voltage may substantially minimize power consumption. The minimum operating voltage for individual flash memory devices may vary from IC to IC, by manufacturing lot, and by manufacturer. In a product, the minimum operating voltage for a particular flash memory may be determined, for example, by a controller built-in to a flash memory reporting (automatically or in response to a query) the minimum operating voltage (e.g., 2.5 V, 3.15 V) to a memory controller or microprocessor. The stored voltage information may further include information to adjust the operating voltage based on temperature.

Claims

1. A flash memory device, comprising:

a first plurality of memory cells for storing data;

a second plurality of memory cells for storing data;

a voltage input adapted for connection to an output of a voltage-regulated power supply;

a first register containing information indicating a first minimum operating voltage to supply from the voltage-regulated power supply to the voltage input for performing a read operation on one or more of the first plurality of memory cells;

a second register containing information indicating a second minimum operating voltage to supply from the voltage-regulated power supply to the voltage input for performing a read operation on one or more of the second plurality of memory cells; and

a processor configured to i) identify a greatest minimum operating voltage from among the first minimum operating voltage and the second minimum operating voltage, and ii) determine a selected operating voltage to supply from the voltage-regulated power supply to the voltage input for performing the read operation of the one or more of the first plurality of memory cells based upon the identified greatest minimum operating voltage.

2. The flash memory device of claim 1, further comprising:

a temperature sensor configured to measure a temperature associated with the first plurality of memory cells; and

wherein the processor is configured to further determine the selected operating voltage to supply from the voltage-regulated power supply to the voltage input for performing the read operation of the one or more of the first plurality of memory cells based upon the temperature measured by the temperature sensor.

3. The flash memory device of claim 1, wherein the processor is further configured to determine the selected operating voltage in response to a start-up of the flash memory device, in response to receiving a read command or a write command for the first plurality of memory cells, or on a recurring basis during operation of the flash memory device.

4. The flash memory device of claim 1, wherein the processor is configured to further determine the selected operating voltage based upon a voltage margin above the greatest minimum operating voltage for reliably operating at least the first memory cells.

5. The flash memory device of claim 4, wherein the voltage margin is based at least in part upon circuit load dynamics associated with at least the first plurality of memory cells.

6. The flash memory device of claim 4, wherein the voltage margin is based at least in part upon a capacitance associated with at least the first plurality of memory cells.

7. The flash memory device of claim 4, wherein the voltage margin is based at least in part upon transient response characteristics associated with the power supply.

8. A method of supplying power to a flash memory device, the method comprising:

receiving information indicating a first minimum operating voltage to supply from a voltage-regulated power supply to a voltage input for performing a read operation on one or more of a first plurality of memory cells;

receiving information indicating a second minimum operating voltage to supply from the voltage-regulated power supply to the voltage input for performing a read operation on one or more of a second plurality of memory cells;

receiving a command to read data that is stored in the first plurality of memory cells of the flash memory device;

selecting a greatest minimum operating voltage from among the first minimum operating voltage and the second minimum operating voltage;

setting an output voltage from the voltage-regulated supply to the voltage input for performing the command to read data based upon the received information indicating the first minimum operating voltage and based upon the selected greatest minimum operating voltage; and

executing the command to read the data using the set output voltage.

9. The method of claim 8, wherein the output voltage is further set based upon a voltage margin above the greatest minimum operating voltage for reliably operating at least the first memory cells.

10. The method of claim 9, wherein the voltage margin is based at least in part upon circuit load dynamics associated with at least the first memory cells.

11. The method of claim 9, wherein the voltage margin is based at least in part upon a capacitance associated with at least the first memory cells.

12. The method of claim 9, wherein the voltage margin is based at least in part upon transient response characteristics associated with the power supply.

13. The method of claim 8, further comprising:

receiving a temperature measurement associated with the first plurality of memory cells; and

wherein the output voltage is further set based upon the received temperature measurement.

14. The method of claim 8, wherein setting the output voltage is further performed in response to the flash memory device starting-up or on a recurring basis during operation of the flash memory device.

15. A computer program product tangibly embodied in a machine-readable storage device, the computer program product containing instructions that, when executed, cause a processor to perform operations to supply power to a flash memory device, the operations comprising:

receiving information indicating a first minimum operating voltage to supply from a voltage-regulated power supply to a voltage input for performing a read operation on one or more of a first plurality of memory cells;

receiving information indicating a second minimum operating voltage to supply from the voltage-regulated power supply to the voltage input for performing a read operation on one or more of a second plurality of memory cells;

receiving a command to read data that is stored in the first plurality of memory cells of the flash memory device;

selecting a greatest minimum operating voltage from among the first minimum operating voltage and the second minimum operating voltage;

sending a signal to the voltage-regulated supply to supply an output voltage to the voltage input for performing the command to read data, wherein the output voltage is determined based upon the selected greatest minimum operating voltage; and

executing the command to read the data using the set output voltage.

16. The computer program product of claim 15, wherein the output voltage is further determined based upon a voltage margin above the greatest minimum operating voltage for reliably operating at least the first memory cells.

17. The computer program product of claim 16, wherein the voltage margin is based at least in part upon circuit load dynamics associated with at least the first memory cells.

18. The computer program product of claim 16, wherein the voltage margin is based at least in part upon a capacitance associated with at least the first memory cells.

19. The computer program product of claim 16, wherein the voltage margin is based at least in part upon transient response characteristics associated with the power supply.

20. The computer program product of claim 15, wherein the operations further comprise:

receiving a temperature measurement associated with the first plurality of memory cells; and

wherein the output voltage is further determined based upon the received temperature measurement.