System to improve memory reliability and associated methods

• US 8,171,377 B2
• Filed: 01/31/2008
• Issued: 05/01/2012
• Est. Priority Date: 01/31/2008
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Dell, Timothy J., Lastras-Montano, Luis A., Trager, Barry M., Winograd, Shmuel
• Primary Examiner(s): Alphonse, Fritz
• Application Number:
  US12/023,374
• Publication Number:
  US 20100287445A1
• Time in Patent Office: 1,552 Days
• Field of Search: 714/763, 714/756, 714/762, 714/755, 714/785
• US Class Current: 714/763
• CPC Class Codes: G06F 11/1044 with specific ECC/EDC distribution
• CPC Class Codes: H03M 13/1515 Reed-Solomon codes
• CPC Class Codes: H03M 13/1545 Determination of error locations, e.g. Chien search or other methods or arrangements for the determination of the roots of the error locator polynomial

Abstract

A system to improve memory reliability in computer systems that may include memory chips, and may rely on a error control encoder to send codeword symbols for storage in each of the memory chips. At least two symbols from a codeword are assigned to each memory chip and therefore failure of any of the memory chips could affect two symbols or more. The system may also include a table to record failures and partial failures of the codeword symbols for each of the memory chips so the error control encoder can correct subsequent partial failures based upon the previous partial failures. The error control coder is capable of correcting and/or detecting more errors if only a fraction of a chip is noted in the table as having a failure as opposed to a full chip noted as having a failure.

Claims

1. A system to improve memory reliability, the system comprising:

memory chips;

an error control encoder to send codeword symbols for storage in each of said memory chips;

an error control decoder to read codeword symbols from the said memory chips, where at least two distinct symbols of the codeword are assigned to each of said memory chips; and

a table to record failures and partial failures of the codeword symbols for each of said memory chips so said error control encoder can correct subsequent partial failures based upon the previous partial failures.

2. The system of claim 1 wherein said error control decoder detects more errors if previously a portion of one of said memory chips failed rather than a total failure of one of said memory chips.

3. The system of claim 1 wherein each of said memory chips have input pins and output pins.

4. The system of claim 3 wherein an error isolated to one of the input pins or output pins in each of said memory chips affects at most one codeword symbol.

5. The system of claim 1 wherein if the number of codeword symbols affected by failures is sufficiently small, then new failures can be corrected.

6. The system of claim 1 wherein the error control decoder performs erasure decoding based upon the recorded failures.

7. The system of claim 1 wherein said error

control encoder uses a Reed-Solomon code to produce the codeword symbols.

8. A computer processor implemented method to improve memory reliability, the method comprising:

sending, by the computer processor, codeword symbols for storage in each of a plurality of memory chips where at least two codeword symbols are assigned to each of the memory chips; and

recording, by the computer processor, failures and partial failures of the codeword symbols for each of the plurality of memory chips so subsequent partial failures can be corrected based upon the previous partial failures.

9. The method of claim 8 wherein more errors are detected if previously a portion of one of the plurality of memory chips failed rather than total failure of one of the plurality of memory chips.

10. The method of claim 8 wherein at most one codeword symbol is affected when an error to one of an input pin or output pin in one of the plurality of memory chips is isolated.

11. The method of claim 8 wherein if the number of codeword symbols affected by failures is sufficiently small, then new failures can be corrected.

12. The method of claim 8 further comprising performing erasure decoding based upon the recorded failures.

13. The method of claim 8 wherein the codeword symbols are produced using a Reed-Solomon code.

14. A computer program product embodied in a tangible media comprising:

computer readable program codes coupled to the tangible media to improve memory reliability, the computer readable program codes configured to cause the program to;

send codeword symbols for storage in each of a plurality of memory chips where at least two symbols from the codeword are assigned to each of the memory chips; and

record failures and partial failures of the codeword symbols for each of the plurality of memory chips so subsequent partial failures can be corrected based upon the previous partial failures.

15. The computer program product of claim 14 further comprising program code configured to:

detect more errors if previously a portion of one of the plurality of memory chips failed rather than total failure of one of the plurality of memory chips.

16. The computer program product of claim 14 further comprising program code configured to:

affect at most one codeword symbol when an error to one of an input pin or output pin in one of the plurality of memory chips is isolated.

17. The computer program product of claim 14 further comprising program code configured to:

correcting new failures if the number of codeword symbols affected by the failures is sufficiently small.

18. The computer program product of claim 14 further comprising program code configured to:

perform erasure decoding based upon the recorded failures.

19. The computer program product of claim 14 further comprising program code configured to:

use a Reed-Solomon code to produce the codeword symbols.