Single event upset error detection within sequential storage circuitry of an integrated circuit

• US 8,171,386 B2
• Filed: 03/27/2008
• Issued: 05/01/2012
• Est. Priority Date: 03/27/2008
• Status: Active Grant

• Current Assignee: Arm Ltd. (United Kingdom) (SoftBank Group Corp.)
• Original Assignee: Arm Ltd. (United Kingdom) (SoftBank Group Corp.)
• Inventors: Chandra, Vikas, Idgunji, Sachin Satish
• Primary Examiner(s): DUNCAN, MARC M
• Application Number:
  US12/078,189
• Publication Number:
  US 20090249175A1
• Time in Patent Office: 1,496 Days
• Field of Search: 714/11, 714/12, 714/822
• US Class Current: 714/822
• CPC Class Codes: G06F 11/00 Error detection; Error correction; Monitoring error detection, correction or monitoring in information storage based on relative movement between record carrier and transducer G11B20/18; monitoring, i.e. supervising the progress of recording or reproducing G11B27/36; in static stores G11C29/00

Abstract

Sequential storage circuitry for a integrated circuit is provided, comprising a first storage element, a second storage element and an additional storage element. The first storage element stores, during a first phase of a clock signal, a first indication of an input data value received by the sequential storage circuitry. The second storage element is coupled to an output of the first storage element, and stores a second indication of the input data value during a second phase of the clock signal. The additional storage element is driven by a pulse signal derived from the clock signal, and is arranged on occurrence of that pulse signal to store a third indication of the input data value. Error detection circuitry is then provided for detecting a single event upset error in either the first storage element or the second storage element. In particular, during the first phase of the clock signal, the error detection circuitry detects the single event upset error in the first storage element if there is a difference in the input data value as indicated by the first indication and the third indication. Further, during the second phase of the clock signal, the error detection circuitry detects a single event upset error in the second storage element if there is a difference in the input data value as indicated by the second indication and the third indication. Such an arrangement provides a simple mechanism for detecting soft errors in both the first storage element and the second storage element using only one additional storage element.

Claims

1. Sequential storage circuitry for an integrated circuit, comprising:

a first storage element for storing, during a first phase of a clock signal, a first indication of an input data value received by the sequential storage circuitry;

a second storage element coupled to an output of the first storage element, for storing a second indication of the input data value during a second phase of the clock signal;

an additional storage element for storing a third indication of the input data value on occurrence of a pulse signal derived from the clock signal; and

error detection circuitry for detecting a single event upset error in either the first storage element or the second storage element by;

(i) during the first phase of the clock signal, detecting the single event upset error in the first storage element if there is a difference in the input data value as indicated by said first indication and said third indication; and

(ii) during the second phase of the clock signal, detecting the single event upset error in the second storage element if there is a difference in the input data value as indicated by said second indication and said third indication.

2. Sequential storage circuitry as claimed in claim 1, wherein the error detection circuitry is arranged to generate an error signal on detection of said single event upset error, but is arranged to suppress generation of the error signal during the occurrence of said pulse signal.

3. Sequential storage circuitry as claimed in claim 2, wherein the pulse signal is generated in response to the start of the first phase of the clock signal, and no error signal is produced for any single event upset error occurring in the first storage element during occurrence of the pulse signal.

4. Sequential storage circuitry as claimed in claim 2, wherein the pulse signal is generated just prior to the end of the second phase of the clock signal, and no error signal is produced for any single event upset error occurring in the second storage element during occurrence of the pulse signal.

5. Sequential storage circuitry as claimed in claim 2, wherein the value of the error signal output by the error detection circuitry is latched immediately before generation of the pulse signal.

6. Sequential storage circuitry as claimed in claim 1, wherein:

said additional storage element is operable in either a single event upset error detection mode or a state retention mode;

in the single event upset error detection mode the additional storage element storing the third indication of the input data value on occurrence of the pulse signal derived from the clock signal; and

in the state retention mode, the additional storage element being arranged to store an indication of the input data value when power is removed from the first and second storage elements but not the additional storage element, the error detection circuitry not being used in the state retention mode.

7. Sequential storage circuitry as claimed in claim 1, wherein the additional storage element is designed to be robust to single event upset errors, thereby reducing the likelihood of the error detection circuitry detecting a difference in the input data value due to a single event upset error occurring in the additional storage element.

8. Sequential storage circuitry as claimed in claim 1, wherein:

the error detection circuitry is coupled to an output of the second storage element;

during the first phase of the clock signal, the second storage element being transparent such that the output of the second storage element during the first phase of the clock cycle represents the first indication of the data value stored in the first storage element, whereby the error detection circuitry is arranged to detect a single event upset error in the first storage element during said first phase of the clock signal;

during the second phase of the clock signal, the second storage element being opaque such that the output of the second storage element during the second phase of the clock cycle represents the second indication of the data value stored in the second storage element, whereby the error detection circuitry is arranged to detect a single event upset error in the second storage element during said second phase of the clock signal.

9. Sequential storage circuitry as claimed in claim 1, further comprising:

pulse generation circuitry for generating the pulse signal from a predetermined clock edge of the clock signal.

10. An integrated circuit comprising a plurality of sequential storage circuits interposed by combinatorial circuitry, at least one of the sequential storage circuits comprising:

a first storage element for storing, during a first phase of a clock signal, a first indication of an input data value received by the sequential storage circuit;

a second storage element coupled to an output of the first storage element, for storing a second indication of the input data value during a second phase of the clock signal;

an additional storage element for storing a third indication of the input data value on occurrence of a pulse signal derived from the clock signal; and

error detection circuitry for detecting a single event upset error in either the first storage element or the second storage element by;

(i) during the first phase of the clock signal, detecting the single event upset error in the first storage element if there is a difference in the input data value as indicated by said first indication and said third indication; and

(ii) during the second phase of the clock signal, detecting the single event upset error in the second storage element if there is a difference in the input data value as indicated by said second indication and said third indication.

11. An integrated circuit as claimed in claim 10, wherein the error detection circuitry is arranged to generate an error signal on detection of said single event upset error, but is arranged to suppress generation of the error signal during the occurrence of said pulse signal, the integrated circuit further comprising:

an error signal latch coupled to the output of each of said at least one of the sequential storage circuits, said error latch being arranged to latch the value of the error signal output by the error detection circuitry immediately before generation of the pulse signal.

12. A method of detecting a single event upset in sequential storage circuitry of an integrated circuit, the sequential storage circuitry comprising a first storage element, a second storage element coupled to an output of the first storage element, and an additional storage element, the method comprising the steps of:

storing in the first storage element, during a first phase of a clock signal, a first indication of an input data value received by the sequential storage circuitry;

storing in the second storage element, during a second phase of the clock signal, a second indication of the input data value;

storing in the additional storage element, on occurrence of a pulse signal derived from the clock signal, a third indication of the input data value; and

detecting a single event upset error in either the first storage element or the second storage element by;

(i) during the first phase of the clock signal, detecting the single event upset error in the first storage element if there is a difference in the input data value as indicated by said first indication and said third indication; and

(ii) during the second phase of the clock signal, detecting the single event upset error in the second storage element if there is a difference in the input data value as indicated by said second indication and said third indication.