Integrated circuit structure incorporating an inductor, an associated design method and an associated design system

• US 8,171,435 B2
• Filed: 03/10/2010
• Issued: 05/01/2012
• Est. Priority Date: 03/29/2007
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: He, Zhong-Xiang, Rassel, Robert M., Voldman, Steven H.
• Primary Examiner(s): Whitmore, Stacy
• Application Number:
  US12/720,728
• Publication Number:
  US 20100175035A1
• Time in Patent Office: 783 Days
• Field of Search: 716100-101, 716/115, 716118-119, 716/122, 716132-133, 716/136
• US Class Current: 716/100
• CPC Class Codes: G06F 30/36 Circuit design at the analogue level
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

Disclosed are embodiments of a circuit (e.g., an electrostatic discharge (ESD) circuit), a design methodology and a design system. In the circuit, an ESD device is wired to a first metal level (e.g., M1). An inductor is formed in a second metal level (e.g., M5) above the first metal level and is aligned over and electrically connected in parallel to the ESD device by a single vertical via stack. The inductor is configured to nullify, for a given application frequency, the capacitance value of the ESD device. The quality factor of the inductor is optimized by providing, on a third metal level (e.g., M3) between the second metal level and the first metal level, a shield to minimize inductive coupling. An opening in the shield allows the via stack to pass through, trading off Q factor reduction for size-scaling and ESD robustness improvements.

Claims

1. A computer-implemented method for designing an integrated circuit structure, said method comprising:

receiving, by a computer, design parameters for an electrostatic discharge circuit and a specified application frequency, wherein said electrostatic discharge circuit comprises an electrostatic discharge device electrically connected in parallel to an inductor;

generating, by said computer, a first design for said electrostatic discharge device based on said design parameters;

determining, by said computer and based on said first design, a capacitance value for said electrostatic discharge device;

determining, by said computer and based on said capacitance value and said application frequency, an inductance value for said inductor to ensure that a subsequently designed inductor-capacitor (LC) circuit will have a resonant frequency at said application frequency; and

generating, by said computer, a second design comprising said inductor with said inductance value aligned over and electrically connected to said electrostatic discharge device of said first design to form said inductor-capacitor circuit.

2. The method of claim 1, wherein said determining of said capacitance value comprises:

accessing a table of capacitance values according to device sizes and types; and

determining said capacitance value based on a type and size of said electrostatic discharge device as specified by said first design.

3. The method of claim 1, wherein said determining of said inductance value comprises solving for one over a product of a capacitance value of said electrostatic discharge device and said specified application frequency squared.

4. The method of claim 1, wherein said generating of said second design comprises selecting a diameter of a planar conductive coil for said inductor, a shape of said coil, a number of turns in said coil and a length of said coil sufficient to achieve said inductance value.

5. The method of claim 1,

wherein said receiving of said design parameters comprises receiving a specified current density, and

wherein said method further comprises:

determining, by said computer, a minimum wire width for said inductor that is sufficient to sustain said specified current density without failure; and

generating, by said computer, said second design so that said inductor has no less than said minimum wire width.

6. The method of claim 1,

wherein said generating of said first design comprises generating said first design such that said electrostatic discharge device is wired to a first metal level above said electrostatic discharge device,

wherein said generating of said second design comprises generating said second design such that said inductor comprises a planar conductive coil in a second metal level above and parallel to said first metal level and such that a first end of said coil is electrically connected to said first metal level by a conductor extending vertically from said first end to said first metal level such that said conductor is perpendicular to said inductor.

7. The method of claim 6, further comprising generating, by said computer, a third design comprising a shield in a third metal level between and parallel to said first metal level and said second metal level,

wherein said shield is configured to minimize inductive coupling between said inductor and said electrostatic discharge device of said second design and comprises an opening through which said conductor extends perpendicular to said shield.

8. The method of claim 1, wherein said generating of said first design, said generating of said second design and said generating of said third design comprise using a design kit comprising hierarchical parameterized cells for electronic components of electrostatic discharge devices, inductors, and shields.

9. A program storage device readable by computer and tangibly embodying a program of instructions executable by said computer to perform a method of designing an integrated circuit structure, said method comprising:

receiving design parameters for an electrostatic discharge circuit and a specified application frequency, wherein said electrostatic discharge circuit comprises an electrostatic discharge device electrically connected in parallel to an inductor;

generating a first design for said electrostatic discharge device based on said design parameters;

determining, based on said first design, a capacitance value for said electrostatic discharge device;

determining, based on said capacitance value and said application frequency, an inductance value for said inductor to ensure that a subsequently designed inductor-capacitor (LC) circuit will have a resonant frequency at said application frequency; and

generating a second design comprising said inductor with said inductance value aligned over and electrically connected to said electrostatic discharge device of said first design to form said inductor-capacitor circuit.

10. The program storage device of claim 9, wherein said determining of said capacitance value comprises:

accessing a table of capacitance values according to device sizes and types; and

determining said capacitance value based on a type and size of said electrostatic discharge device as specified by said first design.

11. The program storage device of claim 9, wherein said generating of said second design comprises selecting a diameter of a planar conductive coil for said inductor, a shape of said coil, a number of turns in said coil and a length of said coil sufficient to achieve said inductance value.

12. The program storage device of claim 9,

wherein said receiving of said design parameters comprises receiving a specified current density, and

wherein said method further comprises:

determining a minimum wire width for said inductor that is sufficient to sustain said specified current density without failure; and

generating said second design so that said inductor has no less than said minimum wire width.

13. The program storage device of claim 9,

wherein said generating of said first design comprises generating said first design such that said electrostatic discharge device is wired to a first metal level above said electrostatic discharge device, and

wherein said generating of said second design comprises generating said second design such that said inductor comprises a planar conductive coil in a second metal level above and parallel to said first metal level and such that a first end of said coil is electrically connected to said first metal level by a conductor extending vertically from said first end to said first metal level perpendicular to said inductor.

14. The program storage device of claim 13,

wherein said method further comprises generating a third design comprising a shield in a third metal level between and parallel to said first metal level and said second metal level, and

wherein said shield is configured to minimize inductive coupling between said inductor and said electrostatic discharge device of said second design and comprises an opening through which said conductor extends perpendicular to said shield.

15. A computer-aided design system for designing an integrated circuit, said system comprising:

a user interface for receiving design parameters for an electrostatic discharge circuit and a specified application frequency, wherein said electrostatic discharge circuit comprises an electrostatic discharge device electrically connected in parallel to an inductor; and

at least one processor adapted to generate a first design for said electrostatic discharge device based on said design parameters,

wherein said processor is further adapted;

to determine, based on said first design, a capacitance value for said electrostatic discharge device;

to determine, based on said capacitance value and said application frequency, an inductance value for said inductor to ensure that a subsequently designed inductor-capacitor (LC) circuit will have a resonant frequency at said application frequency; and

to generate a second design comprising said inductor with said inductance value aligned over and electrically connected to said electrostatic discharge device of said first design to form said inductor-capacitor circuit.

16. The design system of claim 15, further comprising a storage device comprising a table of capacitance values according to device sizes and types,

wherein said first design comprises a type and size for said electrostatic discharge device, and

wherein said processor is further adapted to access said table in order to determine said capacitance value of said electrostatic discharge device based on said type and said size of said electrostatic discharge device.

17. The design system of claim 15, wherein said processor is further adapted to determine said inductance value by solving for one over a product of a capacitance value of said electrostatic discharge device and said specified application frequency squared.

18. The design system of claim 15, wherein said processor is further adapted to generate said second design such that said inductor comprises a planar conductive coil with a shape, a diameter, a number of turns and a length sufficient to achieve said inductance value.

19. The design system of claim 15,

wherein said design parameters comprise a specified current density, and

wherein said processor is further adapted to determine a minimum wire width for said inductor that is sufficient to sustain said specified current density without failure and further to generate said second design so that said inductor has no less than said minimum wire width.

20. The design system of claim 15, wherein said processor is further adapted:

to generate said first design such that said electrostatic discharge device is wired to a first metal level above said electrostatic discharge device, and

to generate said second design such that said inductor comprises a planar conductive coil in a second metal level above and parallel to said first metal level and such that a first end of said coil is electrically connected to said first metal level by a conductor extending vertically from said first end to said first metal level perpendicular to said inductor.