Timing analyzing apparatus, timing analyzing method and program thereof
First Claim
1. A timing analyzing apparatus, comprising:
- a storage apparatus which stores a global clock list including information on clock paths inside and outside a partial area of an electronic circuit, and a post layout processing area netlist which is a netlist of the partial area after layout processing of circuits therein is executed; and
a timing analyzing unit which recognizes a clock path between a clock source located outside the partial area and one of two points on the circuits located in the partial area, another clock path located between the clock source and the other point of the two points on the circuits located in the partial area and a common part that exists outside the partial area and is common in the two clock paths; and
performs a CRPR calculation between the two points wherein clock delay of the common part is purposefully neglected, to judge whether the delay of a clock path and a signal path of the electronic circuit satisfies timing constraints using the calculated clock skew.
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Abstract
A timing analyzing apparatus according to an exemplary aspect of the invention includes, a storage apparatus which stores a global clock list including information on clock paths inside and outside a partial area of an electronic circuit, and a post layout processing area netlist which is a netlist of the partial area after layout processing of circuits therein is executed; and a timing analyzing unit which calculates the clock skew between two points on the circuits in the partial area, neglecting the clock delay of a common part outside thereof of two clock paths from the clock source, located outside thereof in the electronic circuit, to the two points (CRPR calculation), to judge whether the delay of a clock path and a signal path of the electronic circuit satisfies timing constraints using the calculated clock skew.
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Citations
16 Claims
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1. A timing analyzing apparatus, comprising:
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a storage apparatus which stores a global clock list including information on clock paths inside and outside a partial area of an electronic circuit, and a post layout processing area netlist which is a netlist of the partial area after layout processing of circuits therein is executed; and a timing analyzing unit which recognizes a clock path between a clock source located outside the partial area and one of two points on the circuits located in the partial area, another clock path located between the clock source and the other point of the two points on the circuits located in the partial area and a common part that exists outside the partial area and is common in the two clock paths; and
performs a CRPR calculation between the two points wherein clock delay of the common part is purposefully neglected, to judge whether the delay of a clock path and a signal path of the electronic circuit satisfies timing constraints using the calculated clock skew. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A timing analyzing apparatus, comprising:
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a first means for storing a global clock list including information on clock paths inside and outside a partial area of an electronic circuit, and a post layout processing area netlist which is a netlist of the partial area after layout processing of circuits therein is executed; and a second means for recognizing a clock path between a clock source located outside the partial area and one of two points on the circuits located in the partial area, another clock path located between the clock source and the other point of the two points on the circuits located in the partial area and a common part that exists outside the partial area and is common in the two clock paths; and
performing a CRPR calculation between the two points wherein clock delay of the common part is purposefully neglected, to judge whether the delay of a clock path or a signal path of the electronic circuit satisfies timing constraints using the calculated clock skew. - View Dependent Claims (9, 10)
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11. A timing analyzing method, comprising:
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storing a global clock list including information on clock paths inside and outside a partial area of an electronic circuit, and a post layout processing area netlist which is a netlist of the partial area after layout processing of circuits therein is executed; recognizing using a computer a clock path between a clock source located outside the partial area and one of two points on the circuits located in the partial area, another clock path located between the clock source and the other point of the two points on the circuits located in the partial area and a common part that exists outside the partial area and is common in the two clock paths; and performing using the computer a CRPR calculation between the two points wherein clock delay of the common part is purposefully neglected, to judge whether the delay of a clock path and a signal path of the electronic circuit satisfies timing constraints using the calculated clock skew. - View Dependent Claims (12, 13)
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14. A non-transitory computer-readable recording medium recording thereon a program which makes a computer function as:
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a storage apparatus which stores a global clock list including information on clock paths inside and outside a partial area of an electronic circuit, and a post layout processing area netlist which is a netlist of the partial area after layout processing of circuits therein is executed; and a timing analyzing unit which recognizes a clock path between a clock source located outside the partial area and one of two points on the circuits located in the partial area, another clock path located between the clock source and the other point of the two points on the circuits located in the partial area and a common part that exists outside the partial area and is common in the two clock paths; and
performs a CRPR calculation between the two points wherein clock delay of the common part is purposefully neglected, to judge whether the delay of a clock path and a signal path of the electronic circuit satisfies timing constraints using the calculated clock skew. - View Dependent Claims (15, 16)
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Specification