Method for fabricating micro-electro-mechanical system (MEMS) device

• US 8,173,471 B2
• Filed: 04/29/2008
• Issued: 05/08/2012
• Est. Priority Date: 04/29/2008
• Status: Active Grant

• Current Assignee: Solid State System Co., Ltd.
• Original Assignee: Solid State System Co., Ltd.
• Inventors: Hsieh, Tsung-Min, Lee, Chien-Hsing
• Primary Examiner(s): Lebentritt, Michael
• Assistant Examiner(s): Kusumakar, Karen
• Application Number:
  US12/111,208
• Publication Number:
  US 20110104844A1
• Time in Patent Office: 1,470 Days
• Field of Search: 438 50- 53, 257415-420
• US Class Current: 438/53
• CPC Class Codes: B81B 2201/0235 Accelerometers
• CPC Class Codes: B81B 2207/015 the micromechanical device and the control or processing electronics being integrated on the same substrate
• CPC Class Codes: B81C 1/00246 Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate
• CPC Class Codes: B81C 2203/0714 Forming the micromechanical structure with a CMOS process
• CPC Class Codes: B81C 2203/0735 Post-CMOS, i.e. forming the micromechanical structure after the CMOS circuit
• CPC Class Codes: G01P 15/0802 Details
• CPC Class Codes: G01P 15/125 by capacitive pick-up

Abstract

A method for fabricating MEMS device includes providing a substrate having a first side and a second side. Then, a structural dielectric layer is formed over the substrate at the first side, wherein a structural conductive layer is embedded in the structural dielectric layer. A multi-stage patterning process is performed on the substrate from the second side, wherein a plurality of regions of the substrate with different levels is formed and a portion of the structural dielectric layer is exposed. An isotropic etching process is performed from the second side of the substrate or from the both side of the substrate to etch the structural dielectric layer, wherein a remaining portion of the structural dielectric layer comprises the structural conductive layer and a dielectric portion enclosed by the structural conductive layer.

Claims

1. A method for fabricating micro-electro-mechanical system (MEMS) device, comprising:

providing a substrate as a single crystal substrate, having a first side and a second side, and having a MEMS region and an integrated-circuit (IC) region;

forming a structural dielectric layer over the first side of the substrate, wherein the IC region has a circuit structure with an interconnection structure formed in the structural dielectric layer;

performing a multi-stage patterning process on the substrate at the MEMS region from the second side to form a plurality of mass blocks of single crystal with different levels, wherein a portion of the structural dielectric layer is exposed; and

performing an isotropic etching process at the MEMS region to etch the structural dielectric layer over the single crystal mass blocks, wherein the mass blocks are released to form a MEMS structure.

2. The method of claim 1, wherein the step of performing a multi-stage patterning process on the substrate comprises:

forming a mask layer on the substrate at the second side;

patterning the mask layer to expose the substrate at a first region and a second region; and

patterning the substrate to expose the portion of the structural dielectric layer, wherein the substrate at the second side has multiple regions with different levels of height.

3. The method of claim 2, wherein the step of patterning the substrate comprises:

forming an etching mask pattern on the mask layer and on the substrate at the second region and a portion of the first region, wherein a portion of the substrate at the first region is exposed;

etching the exposed portion of the substrate with a depth;

removing the etching mask pattern wherein the etching mask pattern remains; and

performing an anisotropic etching process with the etching mask pattern as a mask to expose the structural dielectric layer.

4. The method of claim 3, wherein the mask layer is a dielectric layer or a metal mask layer.

5. The method of claim 1, wherein the step of performing the multi-stage patterning process on the substrate comprises:

patterning the substrate at the second side to have a plurality indent regions with a depth;

forming an etching mask layer on the substrate other than the indent regions; and

performing an anisotropic etching process with the etching mask layer to expose the portion of the structural dielectric layer.

6. The method of claim 1, wherein the step of performing the multi-stage patterning process on the substrate comprises:

forming a hard mask layer on the substrate at the second side with multiple levels of height;

patterning the hard mask layer to expose a portion of the substrate, wherein a remaining portion of the hard mask layer has multiple regions with different levels of height;

forming an etching mask pattern on the substrate;

etching the substrate at the second side to form a plurality of indent regions with a depth;

removing the etching mask pattern;

performing an anisotropic etching process on the substrate to expose the structural dielectric layer;

removing a portion of the hard mask layer in thickness for exposing the substrate underneath; and

etching the substrate to produce additional level of height.

7. The method of claim 6, further removing a remaining portion of the hard mask layer.

8. The method of claim 6, wherein the step of forming the hard mask layer comprises:

forming a first hard mask layer on the substrate;

patterning the first hard mask layer to expose the substrate at an intended region;

forming a second hard mask layer over the substrate;

patterning the second hard mask layer, wherein the first hard mask layer remains under the second hard mask layer;

forming a photoresist pattern on the substrate and the second hard mask layer with an exposed portion of the substrate within the intended region of the substrate;

performing a first etching process on the exposed portion of the substrate with a depth;

removing the photoresist pattern;

performing a second etching process on the substrate with the first hard mask layer and the second hard mask layer as an etching mask, to expose the structural dielectric layer;

removing the second hard mask layer; and

performing a third etching process on the substrate with the first mask layer as an etching mask.

9. The method of claim 1, wherein the step of performing the multi-stage patterning process on the substrate comprises:

forming a dielectric mask layer on the substrate at the second side;

patterning the dielectric mask layer to expose the substrate; and

patterning the substrate to expose the portion of the structural dielectric layer, wherein the substrate at the second side has multiple regions with different levels of height.

10. The method of claim 9, wherein the step of patterning the substrate comprises:

forming an etching mask pattern on the dielectric mask layer, wherein a portion of the substrate and a portion of the dielectric mask pattern are exposed;

anisotropically etching the exposed portion of the substrate with a depth, not masked by the dielectric mask layer and the etching mask pattern;

etching the exposed dielectric mask layer with an etching mask pattern as a mask; and

performing an anisotropic etching process with the etching mask pattern as a mask to expose the structural dielectric layer.

11. The method of claim 9, wherein the step of patterning the substrate comprises:

forming an etching mask pattern on the dielectric mask layer, wherein a portion of the substrate and a portion of the dielectric mask pattern are exposed;

anisotropically etching the exposed portion of the substrate with a depth, not masked by the dielectric mask layer and etching mask pattern, wherein the exposed portion of the dielectric mask layer is also etched completely; and

performing an anisotropic etching process with the etching mask pattern as a mask to expose the structural dielectric layer.

12. The method of claim 9, wherein the step of patterning the substrate comprises:

forming an etching mask pattern on the dielectric mask layer and the substrate, wherein a portion of the substrate and a portion of the dielectric mask pattern are exposed;

etching the exposed portion of the substrate with a depth, not masked by the dielectric mask layer and the etching mask pattern;

etching the dielectric mask layer with the etching mask pattern as a mask to further expose a portion of the substrate;

performing an anisotropic etching process with the etching mask pattern as a mask to expose the structural dielectric layer;

removing the etching mask pattern; and

performing another etching process on the substrate with the dielectric mask layer as an etching mask.

13. The method of claim 9, wherein the step of patterning the substrate comprises:

forming an etching mask pattern on the dielectric mask layer and the substrate, wherein a portion of the substrate and a portion of the dielectric mask pattern are exposed;

anisotropically etching the exposed portion of the substrate with a depth, not masked by the dielectric mask layer and the etching mask pattern, wherein the exposed portion of the dielectric mask layer is also etched completely;

performing an anisotropic etching process with the etching mask pattern as a mask to expose the structural dielectric layer;

removing the etching mask pattern; and

performing another etching process on the substrate with the dielectric mask layer as an etching mask.

14. The method of claim 1, wherein the step of forming the structural dielectric layer over the substrate at the first side comprises:

forming a plurality of horizontal metal layers and a plurality vertical metal layers contacting on the mass blocks of single crystal at the MEMS region to serve as at least a part of the MEMS structure.

15. The method of claim 1, wherein the step of forming the structural dielectric layer over the substrate at the first side comprises:

forming a plurality of horizontal metal layers and a plurality vertical metal layers in a plurality of dielectric layers to serve as at least a part of CMOS circuitry.

16. The method of claim 1, wherein the step of forming the structural dielectric layer over the substrate at the first side comprises:

forming an etching stop layer with a pattern on the structural dielectric layer, covering the IC region;

forming a dielectric layer over the structural dielectric layer; and

performing a planarization process on the dielectric layer;

wherein the dielectric layer at top with the structural dielectric layer encloses the etching stop layer.

17. The method of claim 16, wherein the step of planarization process includes Chemical Mechanical Polishing (CMP).

18. The method of claim 16 wherein the etching stop layer is conductive layer, like AL, TiN, or polysilicon.

19. The method of claim 18;

wherein the conductive etching stop layer is electrically connected to substrate.

20. The method of claim 16;

wherein the etching stop layer is dielectric layer layer include SIN, or amorphous Si.

21. The method of claim 1, wherein the step of performing the isotropic etching includes using etchant of Vaper HF.

22. The method of claim 1, in the step of performing the multi-stage patterning process on the substrate, a portion of the mass blocks being isolated from the substrate.

23. The method of claim 1, in the step of performing the multi-stage patterning process on the substrate, a portion of the mass blocks being suspended with respect to the substrate to form a suspension beam structure in the mass blocks, wherein a portion of the mass blocks remains on the substrate.