Semiconductor device and method of manufacturing semiconductor device

• US 8,174,066 B2
• Filed: 08/08/2008
• Issued: 05/08/2012
• Est. Priority Date: 08/10/2007
• Status: Active Grant

• Current Assignee: ROHM Co., Ltd.
• Original Assignee: ROHM Co., Ltd.
• Inventors: Izumi, Naoki
• Primary Examiner(s): Toledo, Fernando L
• Assistant Examiner(s): SINGAL, ANKUSH K
• Application Number:
  US12/222,461
• Publication Number:
  US 20090283823A1
• Time in Patent Office: 1,369 Days
• Field of Search: 257/E29.262, 257/E21.41, 257330-334, 257/374, 257/397, 257513-514, 257/622, 257647-648, 257/135, 257/302, 257/E21.018, 257/E21.036, 257/E21.375, 257/E21.418, 257/E21.447, 257/E21.629, 438/270, 438137-138
• US Class Current: 257/332
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device includes: a semiconductor layer; a first conductivity type region of a first conductivity type formed in a base layer portion of the semiconductor layer; a body region of a second conductivity type formed in the semiconductor layer to be in contact with the first conductivity type region; a trench formed by digging the semiconductor layer from the surface thereof to pass through the body region so that the deepest portion thereof reaches the first conductivity type region; a gate insulating film formed on the bottom surface and the side surface of the trench; a gate electrode buried in the trench through the gate insulating film; a source region of the first conductivity type formed in a surface layer portion of the semiconductor layer on a side in a direction orthogonal to the gate width with respect to the trench to be in contact with the body region; and a high-concentration region of the second conductivity type, formed in the body region on a position opposed to the trench in the direction orthogonal to the gate width, having a higher second conductivity type impurity concentration than that of the periphery thereof.

Claims

1. A semiconductor device comprising:

a semiconductor layer;

a first conductivity type region of a first conductivity type disposed in a base layer portion of the semiconductor layer;

a body region of a second conductivity type disposed in the semiconductor layer so as to be in contact with the first conductivity type region;

a trench extending from a surface of the semiconductor layer to pass through the body region so that a deepest portion of the trench reaches the first conductivity type region;

a gate insulating film disposed on a bottom surface and a side surface of the trench;

a gate electrode having a gate width, and disposed in the trench on the gate insulating film;

a source region of the first conductivity type disposed on a side of the trench in a surface layer portion of the semiconductor layer so as to be in contact with the body region;

a high-concentration region of the second conductivity type disposed in the body region at a position opposed to the trench and having a higher second conductivity type impurity concentration than that of the body region; and

a channel implant region, containing a first conductivity type impurity, disposed in the body region between the trench and the high-concentration region.

2. The semiconductor device according to claim 1, wherein the high-concentration region is disposed adjacent to the side surface of the trench.

3. The semiconductor device according to claim 1, wherein the high-concentration region is disposed under the source region, the high concentration region being closer than the center of the source region to the trench as measured in a direction orthogonal to the gate width.

4. The semiconductor device according to claim 1, wherein a contact region of the second conductivity type passing through the source region to come into contact with the body region is disposed in the surface layer portion of the semiconductor layer, and the high-concentration region is disposed under the contact region.

5. The semiconductor device according to claim 1, wherein the shallowest portion is at the surface of the semiconductor layer.

6. The semiconductor device according to claim 1, wherein the trench has opposing sides that continuously converge towards each other from the shallowest portion to the deepest portion.

7. The semiconductor device according to claim 1, wherein the deepest portion of the trench has a width that is narrower than a width of a shallowest portion of the trench.

8. The semiconductor device according to claim 2, wherein a contact region of the second conductivity type passing through the source region to come into contact with the body region is disposed in the surface layer portion of the semiconductor layer, and the high-concentration region is disposed under the contact region.

9. The semiconductor device according to claim 4, wherein a half of the high-concentration region that is farther from the trench than is the other half of the high-concentration region as measured in a direction orthogonal to the gate width, is arranged under the contact region.

10. The semiconductor device according to claim 4, wherein as measured in a direction orthogonal to the gate width, the high-concentration region has a width, which is the same as a width of the contact region, and is entirely arranged under the contact region.

11. The semiconductor device according to claim 8, wherein a half of the high-concentration region that is farther from the trench than is the other half of the high-concentration region as measured in a direction orthogonal to the gate width, is arranged under the contact region.

12. The semiconductor device according to claim 8, wherein as measured in a direction orthogonal to the gate width, the high-concentration region has a width, which is the same as a width of the contact region, and is entirely arranged under the contact region.