Dual channel trench LDMOS transistors and BCD process with deep trench isolation

• US 8,174,070 B2
• Filed: 12/02/2009
• Issued: 05/08/2012
• Est. Priority Date: 12/02/2009
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Mallikarjunaswamy, Shekar
• Primary Examiner(s): Lebentritt, Michael
• Assistant Examiner(s): KUSUMAKAR, KAREN M
• Application Number:
  US12/629,844
• Publication Number:
  US 20110127602A1
• Time in Patent Office: 888 Days
• Field of Search: 257329-342, 257/E29.183, 257/E29.187, 438/268, 438/270, 438/283
• US Class Current: 257/341
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/8249 Bipolar and MOS technology
• CPC Class Codes: H01L 27/0617 comprising components of the field-effect type H01L27/0251 takes precedence
• CPC Class Codes: H01L 27/0623 in combination with bipolar transistors
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0821 Collector regions of bipolar transistors
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/408 with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
• CPC Class Codes: H01L 29/4175 for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
• CPC Class Codes: H01L 29/42356 Disposition, e.g. buried gate electrode H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/732 Vertical transistors
• CPC Class Codes: H01L 29/7393 Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
• CPC Class Codes: H01L 29/7813 : with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7816 : Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7817 : structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7823 : with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7825 : with trench gate electrode trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7831 : with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645

Abstract

A dual channel trench LDMOS transistor includes a substrate of a first conductivity type; a semiconductor layer of a second conductivity type formed on the substrate; a first trench formed in the semiconductor layer where a trench gate is formed in an upper portion of the first trench; a body region of the first conductivity type formed in the semiconductor layer adjacent the first trench; a source region of the second conductivity type formed in the body region and adjacent the first trench; a planar gate overlying the body region; a drain region of the second conductivity type spaced apart from the body region by a drain drift region. The planar gate forms a lateral channel in the body region, and the trench gate in the first trench forms a vertical channel in the body region of the LDMOS transistor.

Claims

1. A dual channel trench LDMOS transistor, comprising:

a substrate of a first conductivity type;

a semiconductor layer of a second conductivity type formed on the substrate;

a first trench formed in the semiconductor layer, the first trench being filled with a trench dielectric, a trench gate being formed in the first trench and insulated from the sidewall of the first trench by a first gate dielectric layer;

a body region of the first conductivity type formed in the semiconductor layer adjacent the first trench;

a source region of the second conductivity type formed in the body region and adjacent the first trench;

a planar gate insulated from the semiconductor layer by a second gate dielectric layer and overlying the body region, the source region being formed aligned to a first edge of the planar gate; and

a drain region of the second conductivity type formed in the semiconductor layer, the drain region being spaced apart from the body region by a drain drift region,

wherein the planar gate forms a lateral channel of the LDMOS transistor in the body region between the source region and the drain drift region, and the trench gate in the first trench forms a vertical channel of the LDMOS transistor in the body region along the sidewall of the first trench between the source region and the semiconductor layer.

2. The dual channel trench LDMOS transistor of claim 1, wherein the first trench extends only into the semiconductor layer.

3. The dual channel trench LDMOS transistor of claim 1, wherein the first trench extends through the semiconductor layer into the substrate, the trench gate being formed in an upper portion of the first trench.

4. The dual channel trench LDMOS transistor of claim 3, further comprising:

a bottom gate electrode being formed in a lower portion of the first trench and insulated from the sidewall of the first trench by the trench dielectric having a second thickness, the second thickness being greater than the thickness of the first gate dielectric layer insulating the trench gate, the bottom gate electrode being electrically connected to a source potential.

5. The dual channel trench LDMOS transistor of claim 1, further comprising:

a second trench formed in the semiconductor layer and extending into the substrate, the second trench being filled with the trench dielectric,

wherein the second trench encircles active areas of the LDMOS transistor to provide isolation of the LDMOS transistor.

6. The dual channel trench LDMOS transistor of claim 5, further comprising a trench gate being formed in an upper portion of the second trench and insulated from the sidewall of the second trench by a third gate dielectric layer, the trench gate being electrically floating or electrically connected to a given potential for deactivating the trench gate in the second trench.

7. The dual channel trench LDMOS transistor of claim 6, wherein the third gate dielectric layer has a thickness greater than the thickness of the first gate dielectric layer.

8. The dual channel trench LDMOS transistor of claim 1, further comprising:

a second trench formed in the semiconductor layer and extending into the substrate, the second trench being filled with a trench dielectric, a trench gate being formed in an upper portion of the second trench and insulated from the sidewall of the second trench by a third gate dielectric layer, and a bottom gate electrode being formed in a lower portion of the second trench and insulated from the sidewall of the second trench by the trench dielectric, the trench dielectric having a thickness greater than the third gate dielectric layer, the trench gate being electrically floating or electrically connected to a given potential for deactivating the trench gate in the second trench, and the bottom gate electrode being electrically connected to a source potential,

wherein the second trench encircles active areas of the LDMOS transistor to provide isolation of the LDMOS transistor.

9. The dual channel trench LDMOS transistor of claim 8, wherein the third gate dielectric layer has a thickness greater than the thickness of the first gate dielectric layer.

10. The dual channel trench LDMOS transistor of claim 1, wherein the drain drift region comprises a well of the second conductivity type formed in the semiconductor layer.

11. The dual channel trench LDMOS transistor of claim 1, wherein the drain drift region comprises a plurality of wells of the second conductivity type formed in the semiconductor layer, the plurality of wells having different doping concentration levels.

12. The dual channel trench LDMOS transistor of claim 1, further comprising a field oxide layer or a step oxide layer formed in or on a surface of the semiconductor layer between the planar gate and the drain region, the planar gate having a second edge extending over a portion of the field or step oxide layer.

13. The dual channel trench LDMOS transistor of claim 1, wherein the semiconductor layer comprises an epitaxial layer of the second conductivity type.

14. The dual channel trench LDMOS transistor of claim 13, wherein the semiconductor layer further comprises a buried layer of the second conductivity type formed on the substrate, the epitaxial layer being formed on the buried layer.

15. The dual channel trench LDMOS transistor of claim 1, further comprising a plurality of trench fingers formed in the drain drift region, the plurality of trench fingers being filled with a trench dielectric and forming interdigitated trench and drain regions, a trench gate being formed in an upper portion of each of the plurality of trench fingers and insulated from the sidewall of the trench fingers by a third gate dielectric layer, the trench gate being electrically connected to a source potential.

16. The dual channel trench LDMOS transistor of claim 15, wherein the third gate dielectric layer has a thickness greater than the thickness of the first gate dielectric layer.

17. The dual channel trench LDMOS transistor of claim 1, wherein the first trench comprises interdigitated trench regions extending into the source region and the body region to form extensions of the trench gate.

18. The dual channel trench LDMOS transistor of claim 1, further comprising:

a body contact region interposed in the source region for making electrical contact to the body region.

19. The dual channel trench LDMOS transistor of claim 1, wherein the first conductivity type is P-type and the second conductivity type is N-type.

20. The dual channel trench LDMOS transistor of claim 19, further comprising:

a plurality of alternating N-type and P-type regions formed in the drain drift region, the plurality of alternating N-type and P-type regions having higher doping concentration than the drain-drift regions and forming a super junction structure at the drain drift region.

21. The dual channel trench LDMOS transistor of claim 20, wherein the plurality of alternating N-type and P-type regions comprises a first N-type region and a second N-type region and a P-type region sandwiched between the first and second N-type regions, the first and second N-type regions being self-aligned to a second edge of the planar gate and the P-type region being extended to the body region.

22. The dual channel trench LDMOS transistor of claim 20, wherein the plurality of alternating N-type and P-type regions comprises a first P-type region and a second P-type region and an N-type region sandwiched between the first and second P-type regions, the first and second P-type regions and the N-type region being self-aligned to a second edge of the planar gate.

23. A method for forming a dual channel trench LDMOS comprising:

providing a substrate of a first conductivity type;

forming a semiconductor layer of a second conductivity type on the substrate;

forming a first trench in the semiconductor layer, the first trench being filled with a trench dielectric;

forming a trench gate in the first trench, the trench gate being insulated from the sidewall of the first trench by a first gate dielectric layer;

forming a body region of the first conductivity type in the semiconductor layer adjacent the first trench;

forming a source region of the second conductivity type in the body region and adjacent the first trench;

forming a planar gate insulated from the semiconductor layer by a second gate dielectric layer and overlying the body region, the source region being formed aligned to a first edge of the planar gate; and

forming a drain region of the second conductivity type in the semiconductor layer, the drain region being spaced apart from the body region by a drain drift region,

wherein the planar gate forms a lateral channel of the LDMOS transistor in the body region between the source region and the drain drift region, and the trench gate in the first trench forms a vertical channel of the LDMOS transistor in the body region along the sidewall of the first trench between the source region and the semiconductor layer.

24. The method of claim 23, further comprising:

forming a second trench in the semiconductor layer and extending into the substrate, the second trench being filled with the trench dielectric, the second trench encircling active areas of the LDMOS transistor to provide isolation of the LDMOS transistor.