Flat-panel display semiconductor process for efficient manufacturing

• US 8,174,078 B2
• Filed: 11/15/2010
• Issued: 05/08/2012
• Est. Priority Date: 12/09/2008
• Status: Active Grant

• Current Assignee: Xerox Corporation (Xerox Holdings Corp.)
• Original Assignee: Palo Alto Research Center, Inc. (Xerox Holdings Corp.)
• Inventors: Ho, Jackson H., Lu, Jeng Ping
• Primary Examiner(s): Nhu, David
• Application Number:
  US12/946,762
• Publication Number:
  US 20110057193A1
• Time in Patent Office: 540 Days
• Field of Search: 257/59, 257/61, 257/62, 257/63, 257/288, 257/359, 257/E21.17, 257/E21.32, 257/E21.247, 257/E21.267, 257/E21.329, 257/E21.347, 257/E21.411
• US Class Current: 257/359
• CPC Class Codes: H01L 21/268 using electromagnetic radiation, e.g. laser radiation
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/66765 Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate

Abstract

An embodiment is a method and apparatus to fabricate a flat panel display. A poly-last structure is formed for a display panel using an amorphous silicon or amorphous silicon compatible process. The poly-last structure has a channel silicon precursor. The display panel is formed from the poly-last structure using a polysilicon specific or polysilicon compatible process.

Claims

1. A poly-last structure comprising:

a substrate;

a bottom gate deposited on the substrate;

a dielectric layer deposited on the bottom gate;

a doped source and drain regions deposited on the substrate and formed around the bottom gate; and

a channel silicon precursor layer deposited on a patterned doped amorphous silicon layer and the dielectric layer.

2. The poly-last structure of claim 1 wherein the substrate is a glass substrate, a flexible metal, or a plastic substrate.

3. The poly-last structure of claim 1 wherein the doped amorphous silicon layer has a low concentration of hydrogen atoms.

4. The poly-last structure of claim 1 further comprising a passivation layer on the channel silicon precursor layer.

5. A flat panel display comprising:

a substrate; and

a thin film transistor (TFT) array having a plurality of TFTs as pixel switching devices on the substrate, each of the TFTs having a bottom gate structure with polycrystalline silicon and data interconnecting lines, the bottom gate structure and the data interconnecting lines being under a silicon layer.

6. The flat panel display of claim 5 further comprising:

a peripheral driver circuit coupled to the TFT array to drive the pixel switching devices, the peripheral driver circuit having a poly-last architecture.

7. The flat panel display of claim 5 wherein the substrate is a glass substrate, a flexible metal, or a plastic substrate.

8. The flat panel display of claim 5 wherein the bottom gate structure comprises:

a bottom gate deposited on the substrate;

a dielectric layer deposited on the bottom gate;

doped source and drain regions deposited on the substrate and formed around the bottom gate; and

a channel silicon precursor layer deposited on a patterned doped amorphous silicon layer and the dielectric layer.

9. The flat panel display of claim 8 wherein the doped amorphous silicon layer has a low concentration of hydrogen atoms.

10. The flat panel display of claim 8 wherein the bottom gate structure further comprises a passivation layer on the channel silicon precursor layer.