High voltage switching devices and process for forming same

• US 8,174,089 B2
• Filed: 08/06/2010
• Issued: 05/08/2012
• Est. Priority Date: 04/30/2002
• Status: Expired due to Term

• Current Assignee: Wolfspeed, Inc.
• Original Assignee: CREE Incorporated (Wolfspeed, Inc.)
• Inventors: Flynn, Jeffrey S., Brandes, George R., Vaudo, Robert P.
• Primary Examiner(s): Lee, Eugene
• Application Number:
  US12/852,223
• Publication Number:
  US 20100301351A1
• Time in Patent Office: 641 Days
• Field of Search: 257/453, 257/155, 257/194, 257/656
• US Class Current: 257/453
• CPC Class Codes: C30B 25/02 Epitaxial-layer growth
• CPC Class Codes: C30B 29/40 AIIIBV compounds wherein A is B, Al, Ga, In or Tl and B is N, P, As, Sb or Bi
• CPC Class Codes: C30B 29/406 Gallium nitride
• CPC Class Codes: H01L 21/0237 Materials
• CPC Class Codes: H01L 21/0242 Crystalline insulating materials
• CPC Class Codes: H01L 21/02458 Nitrides
• CPC Class Codes: H01L 21/02502 consisting of two layers
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 21/02576 N-type
• CPC Class Codes: H01L 21/02664 Aftertreatments planarisation in general H01L21/304
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/861 Diodes
• CPC Class Codes: H01L 29/868 PIN diodes
• CPC Class Codes: H01L 29/872 Schottky diodes

Abstract

The present invention relates to various switching device structures including Schottky diode, P—N diode, and P—I—N diode, which are characterized by low defect density, low crack density, low pit density and sufficient thickness (>2.5 um) GaN layers of low dopant concentration (<1E16 cm⁻³) grown on a conductive GaN layer. The devices enable substantially higher breakdown voltage on hetero-epitaxial substrates (<2 KV) and extremely high breakdown voltage on homo-epitaxial substrates (>2 KV).

Claims

1. A microelectronic device structure, comprising:

(a) a foreign substrate;

(b) a nucleation buffer layer overlying said foreign substrate;

(c) a first gallium nitride layer overlying said nucleation buffer layer, said first GaN layer having a dopant concentration of not more than about 1×

10¹⁶/cm³;

(d) a second, conductive gallium nitride layer overlying said first gallium nitride layer;

(e) a third gallium nitride layer overlying said second, conductive gallium nitride layer, said third gallium nitride layer having a dopant concentration of not more than about 1×

10¹⁶/cm³; and

(f) at least one metal contact over said third gallium nitride layer, forming a metal-to-semiconductor junction therewith.

2. The microelectronic device structure of claim 1, wherein said foreign substrate comprises a material selected from the group consisting of sapphire, Si, and SiC.

3. The microelectronic device structure of claim 1, wherein said foreign substrate comprises sapphire.

4. The microelectronic device structure of claim 1, wherein the third gallium nitride layer is less than 10 μ

m in thickness.

5. The microelectronic device structure of claim 1, wherein the third gallium nitride layer is less than 20 μ

m in thickness.

6. The microelectronic device structure of claim 1, wherein the third gallium nitride layer is less than 50 μ

m in thickness.

7. The microelectronic device structure of claim 1, wherein the second, conductive gallium nitride layer is doped with a strain-reducing dopant.

8. The microelectronic device structure of claim 1, wherein the second, conductive gallium nitride layer is doped with germanium.

9. The microelectronic device structure of claim 1, wherein the first gallium nitride layer has a thickness of about 0.6 μ

m, wherein the second, conductive gallium nitride layer has a thickness of about 2.0 μ

m and a dopant concentration of about 1.5×

10¹⁹/cm³, and wherein the third gallium nitride layer has a thickness of at least about 2.5 μ

m.

10. The microelectronic device structure of claim 1, wherein the first gallium nitride layer has a thickness of about 0.6 μ

m, wherein the second, conductive gallium nitride layer has a thickness of about 0.5 μ

m and a dopant concentration of about 1.5×

10¹⁹/cm³, and wherein the third gallium nitride layer has a thickness of at least about 2.5 μ

m.

11. The microelectronic device structure of claim 1, wherein said second, conductive gallium nitride layer comprises a first conductive gallium nitride sub-layer of a first dopant concentration and a second conductive gallium nitride sub-layer of a second dopant concentration, wherein said first conductive gallium nitride sub-layer is adjacent to the first gallium nitride layer, wherein said second conductive gallium nitride sub-layer is adjacent to said third gallium nitride layer, and wherein said first dopant concentration is lower than said second dopant concentration.

12. The microelectronic device structure of claim 11, wherein said first gallium nitride layer has a thickness of about 0.6 μ

m, wherein said first conductive gallium nitride sub-layer has a thickness of about 1.9 μ

m and a dopant concentration of about 2.0×

10¹⁸/cm³, wherein said second conductive gallium nitride sub-layer has a thickness of about 0.1 μ

m and a dopant concentration of about 1.5×

10¹⁹/cm³, and wherein said third gallium nitride layer has a thickness of at least about 2.5 μ

m.

13. A microelectronic device structure, comprising:

(a) a foreign substrate;

(b) a nucleation buffer layer overlying said foreign substrate;

(c) a first gallium nitride layer overlying said nucleation buffer layer, said first gallium nitride layer having a dopant concentration of not more than about 1×

10¹⁶/cm³;

(d) a second gallium nitride layer of n-type conductivity, overlying said first gallium nitride layer;

(e) a third gallium nitride layer overlying said second gallium nitride layer of n-type conductivity, said third gallium nitride layer having a dopant concentration of not more than about 1×

10¹⁶/cm³; and

(f) a fourth gallium nitride layer of p-type conductivity, formed over said third gallium nitride layer; and

(g) at least one metal contact overlying said fourth gallium nitride layer.

14. The microelectronic device structure of claim 13, wherein said foreign substrate comprises a material selected from the group consisting of sapphire, Si, and SiC.

15. The microelectronic device structure of claim 13, wherein said foreign substrate comprises sapphire.

16. The microelectronic device structure of claim 13, wherein the third gallium nitride layer is less than 10 μ

m in thickness.

17. The microelectronic device structure of claim 13, wherein the third gallium nitride layer is less than 20 μ

m in thickness.

18. The microelectronic device structure of claim 13, wherein the third gallium nitride layer is less than 50 μ

m in thickness.

19. The microelectronic device structure of claim 13, wherein the second gallium nitride layer of n-type conductivity is doped with a strain-reducing dopant.

20. The microelectronic device structure of claim 13, wherein the second gallium nitride layer of n-type conductivity is doped with germanium.

21. The microelectronic device structure of claim 13, wherein the first gallium nitride layer has a thickness of about 0.6 μ

m, wherein the second gallium nitride layer of n-type conductivity has a thickness of about 2.0 μ

m and a dopant concentration of about 1.5×

10¹⁹/cm³, and wherein the third gallium nitride layer has a thickness of at least about 2.5 μ

m.

22. The microelectronic device structure of claim 13, wherein the first gallium nitride layer has a thickness of about 0.6 μ

m, wherein the second gallium nitride layer of n-type conductivity has a thickness of about 0.5 μ

m and a dopant concentration of about 1.5×

10¹⁹/cm³, and wherein the third gallium nitride layer has a thickness of at least about 2.5 μ

m.

23. The microelectronic device structure of claim 13, wherein said second gallium nitride layer of n-type conductivity comprises a first conductive gallium nitride sub-layer of a first dopant concentration and a second conductive gallium nitride sub-layer of a second dopant concentration, wherein said first conductive gallium nitride sub-layer is adjacent to the first gallium nitride layer, wherein said second conductive gallium nitride sub-layer is adjacent to said third gallium nitride layer, and wherein said first dopant concentration is lower than said second dopant concentration.

24. The microelectronic device structure of claim 23, wherein said first gallium nitride layer has a thickness of about 0.6 μ

m, wherein said first conductive gallium nitride sub-layer has a thickness of about 1.9 μ

m and a dopant concentration of about 2.0×

10¹⁸/cm³, wherein said second conductive gallium nitride sub-layer has a thickness of about 0.1 μ

m and a dopant concentration of about 1.5×

10¹⁹/cm³, and wherein said third gallium nitride layer has a thickness of at least about 2.5 μ

m.