Multichip semiconductor device, chip therefor and method of formation thereof

• US 8,174,093 B2
• Filed: 10/26/2010
• Issued: 05/08/2012
• Est. Priority Date: 12/02/1996
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Hayasaka, Nobuo, Okumura, Katsuya, Sasaki, Keiichi, Matsuo, Mie
• Primary Examiner(s): Graybill, David E
• Application Number:
  US12/926,104
• Publication Number:
  US 20110101522A1
• Time in Patent Office: 560 Days
• Field of Search: None
• US Class Current: 257/621
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/06181 On opposite sides of the body
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/14181 On opposite sides of the body
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 2225/06572 Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 2225/1023 the support being an insulating substrate
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/367 Cooling facilitated by shape of device H01L23/38, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/642 Capacitive arrangements H01L23/49589, H01L23/645, H01L23/647, H01L23/66 take precedence; capacitive effects between wiring layers on the semiconductor body H01L23/5222
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01057 : Lanthanum [La]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/15174 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15192 : Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/1532 : the connection portion being formed on the die mounting surface of the substrate
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA

Abstract

A multichip semiconductor device is disclosed in which chips are stacked each of which comprises a semiconductor substrate formed on top with circuit components and an interlayer insulating film formed on the top of the semiconductor substrate. At least one of the chips has a connect plug of a metal formed in a through hole that passes through the semiconductor substrate and the interlayer insulating film. The chip with the connect plug is electrically connected with another chip by that connect plug.

Claims

1. A multichip semiconductor device having a stack of chips each having a semiconductor substrate which has a surface on which circuit components are formed, wherein at least one chip of the chips includes:

a first interlayer insulating film formed above the surface of the semiconductor substrate,

a connect plug formed entirely in a through hole which passes through the semiconductor substrate and the first interlayer insulating film,

a second interlayer insulating film formed on the first interlayer insulating film, and

a metal interconnection which passes through the second interlayer insulating film and which connects to a portion of the connect plug, an area of the portion being smaller than a cross-sectional area of the connect plug, and

the connect plug of the at least one chip is electrically connected to another chip of the chips.

2. The multichip semiconductor device according to claim 1, wherein the another chip has a connect member that electrically connects with the connect plug.

3. The multichip semiconductor device according to claim 1, wherein the first and second interlayer insulating films are included in a multilevel interconnection layer.

4. The multichip semiconductor device according to claim 3,

wherein the multilevel interconnection layer comprises the first interlayer insulating film formed above the surface of the semiconductor substrate,

the second interlayer insulating film formed on a surface of the first interlayer insulating film,

a pad formed above the second insulating film and electrically connecting with the another chip, and

the metal interconnection which passes through the second interlayer insulating film and which electrically connects the pad to the connect plug.

5. The multichip semiconductor device according to claim 3, wherein the multilevel interconnection layer comprises:

a metal interconnection layer formed above the first interlayer insulating film, and

a metal interconnection which passes through the first interlayer insulating film and which electrically connects the circuit component formed on the surface of the substrate to the metal interconnection layer.

6. The multichip semiconductor device according to claim 1, wherein the connect plug comprises a metal plug formed in the through hole and an insulating film formed between the metal plug and a sidewall of the through hole.

7. The multichip semiconductor device according to claim 1, wherein the first interlayer insulating film covers a MOS transistor formed on the semiconductor substrate.

8. A chip for use in a multichip semiconductor device comprising:

a semiconductor substrate having a surface on which circuit components are formed;

a first interlayer insulating film formed above the surface of the semiconductor substrate;

a connect plug made of a metal formed entirely in a through hole that passes through the first interlayer insulating film and the semiconductor substrate, wherein the connect plug is to be electrically connected to another chip;

a second interlayer insulating film formed on the first interlayer insulating film; and

a metal interconnection which passes through the second interlayer insulating film and which connects to a portion of the connect plug, an area of the portion being smaller than a cross-sectional area of the connect plug.

9. The chip according to claim 8, wherein the connect plug comprises a metal plug formed in the through hole and an insulating film formed between the metal plug and a sidewall of the through hole.

10. The chip according to claim 8, wherein the first interlayer insulating film covers a MOS transistor formed on the semiconductor substrate.

11. A multichip semiconductor device having a stack of chips each having a semiconductor substrate which has a surface on which circuit components are formed, wherein at least one chip of the chips includes:

a first interlayer insulating film formed above the surface of the semiconductor substrate,

a connect plug formed entirely in a through hole which passes through the semiconductor substrate and the first interlayer insulating film,

a second interlayer insulating film formed on the first interlayer insulating film, and a metal interconnection which passes through the second interlayer insulating film and which connects to a portion of the connect plug, an area of the portion being smaller than a cross-sectional area of the connect plug, and

the connect plug of the at least one chip is connected to another chip of the chips.

12. The multichip semiconductor device according to claim 11, wherein the first and second interlayer insulating films are included in a multilevel interconnection layer.

13. The multichip semiconductor device according to claim 12, wherein the multilevel interconnection layer comprises:

the first interlayer insulating film formed above the surface of the semiconductor substrate,

the second interlayer insulating film formed on a surface of the first interlayer insulating film,

a pad formed above the second insulating film and electrically connecting with the another chip, and the metal interconnection which passes through the second interlayer insulating film and which electrically connects the pad to the connect plug.

14. The multichip semiconductor device according to claim 12, wherein the multilevel interconnection layer comprises:

a metal interconnection layer formed above the first interlayer insulating film, and

a metal interconnection which passes through the first interlayer insulating film and which electrically connects the circuit component formed on the surface of the semiconductor substrate to the metal interconnection layer.

15. The multichip semiconductor device according to claim 11, wherein the connect plug comprises a metal plug formed in the through hold and an insulating film formed between the metal plug and a sidewall of the through hole.

16. The multichip semiconductor device according to claim 11, wherein the first interlayer insulating film covers a MOS transistor formed on the semiconductor substrate.