Dummy pattern in wafer backside routing

• US 8,174,124 B2
• Filed: 04/08/2010
• Issued: 05/08/2012
• Est. Priority Date: 04/08/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chiu, Ming-Yen, Chen, Hsien-Wei, Chen, Ming-Fa, Jeng, Shin-Puu
• Primary Examiner(s): Williams, A O
• Application Number:
  US12/756,727
• Publication Number:
  US 20110248404A1
• Time in Patent Office: 761 Days
• Field of Search: 257/773, 257/E23./011, 257/E23.174, 257/E21./585, 257/774, 257/686, 257/706, 257/713, 257/621, 257/690, 257/E23.101, 257/E23.145, 257/E29.166
• US Class Current: 257/773
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2221/6834 used to protect an active side of a device or wafer
• CPC Class Codes: H01L 2221/68372 used to support a device or wafer when forming electrical connections thereto
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05075 Plural internal layers
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05139 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05184 Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/06515 Bonding areas having different functions
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/14181 On opposite sides of the body
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/522 : including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/14 : of a plurality of bump connectors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits

Abstract

A device includes a semiconductor substrate including a front side and a backside. A through-substrate via (TSV) penetrates the semiconductor substrate. A dummy metal line is formed on the backside of the semiconductor substrate, and may be connected to the dummy TSV.

Claims

1. A device comprising:

a semiconductor substrate comprising a front side and a backside;

a through-substrate via (TSV) penetrating the semiconductor substrate; and

a first dummy metal line on the backside of the semiconductor substrate.

2. The device of claim 1 further comprising an active circuit on the front side of the semiconductor substrate, wherein the active circuit comprises a transistor.

3. The device of claim 2 further comprising a dummy TSV penetrating the semiconductor substrate.

4. The device of claim 3, wherein the first dummy metal line is electrically coupled to the dummy TSV, and wherein the first dummy metal line and the dummy TSV are electrically floating.

5. The device of claim 4 further comprising a second dummy metal line on the front side of the semiconductor substrate, wherein the second dummy metal line is electrically coupled to the dummy TSV and the first dummy metal line.

6. The device of claim 4 further comprising:

a plurality of dielectric layers on the backside of the semiconductor substrate;

a plurality of dummy metal lines, with one of the plurality of dummy metal lines in each of the plurality of dielectric layers; and

a plurality of dummy vias electrically coupled to the plurality of dummy metal lines, with the plurality of dummy metal lines, the plurality of dummy vias, and the dummy TSV forming an integrated metal structure.

7. The device of claim 1 further comprising a bond pad on the backside of the semiconductor substrate, and a dummy metal pad at a same level as the bond pad.

8. The device of claim 1 further comprising a dummy via on the backside of the semiconductor substrate and connected to the first dummy metal line.

20. The device of claim 2, wherein the first dummy metal line is electrically floating.

9. A device comprising:

a semiconductor substrate comprising a front side and a backside;

an active circuit on the front side of the semiconductor substrate;

a through-substrate via (TSV) penetrating the semiconductor substrate;

a dummy TSV penetrating the semiconductor substrate; and

a first dummy metal line on the backside of the semiconductor substrate and electrically coupled to the dummy TSV, wherein the first dummy metal line and the dummy TSV are electrically floating.

10. The device of claim 9, wherein the first dummy metal line physically contacts the dummy TSV.

11. The device of claim 9, wherein the semiconductor substrate is a portion of a chip, and wherein the device further comprises:

a bond pad at a back surface of the chip; and

a dummy metal feature at a same level as the bond pad.

12. The device of claim 9 further comprising:

a plurality of dielectric layers on the backside of the semiconductor substrate; and

a plurality of dummy metal features, with each of the plurality of dielectric layers comprising one of the plurality of dummy metal features therein, and wherein the plurality of dummy metal features and the dummy TSV form an integrated metal structure.

13. The device of claim 12 further comprising a plurality of dummy vias, each in one of the plurality of dielectric layers and contacting a respective one of the plurality of dummy metal features.

14. The device of claim 9 further comprising a second dummy metal line on the front side of the semiconductor substrate.

15. The device of claim 14, wherein the second dummy metal line is electrically coupled to the dummy TSV and the first dummy metal line.

16. The device of claim 14 further comprising:

a plurality of dielectric layers on the front side of the semiconductor substrate; and

a plurality of dummy metal features, with each of the plurality of dielectric layers comprising one of the plurality of dummy metal features therein, wherein the plurality of dummy metal features is electrically coupled to the dummy TSV.

17. A device comprising:

a semiconductor substrate comprising a front side and a backside;

an active circuit on the front side of the semiconductor substrate;

a through-substrate via (TSV) penetrating the semiconductor substrate;

a dummy TSV penetrating the semiconductor substrate;

a first plurality of dielectric layers on the backside of the semiconductor substrate;

a first plurality of dummy metal features, with each of the first plurality of dielectric layers comprising one of the first plurality of dummy metal features therein;

a second plurality of dielectric layers on the front side of the semiconductor substrate; and

a second plurality of dummy metal features, with each of the second plurality of dielectric layers comprising one of the second plurality of dummy metal features therein, and wherein the first and the second plurality of dummy metal features and the dummy TSV form an integrated metal structure, and are electrically floating.

18. The device of claim 17 further comprising a bond pad on the backside of the semiconductor substrate, wherein one of the first plurality of dummy metal features is at a same level as the bond pad.

19. The device of claim 17, wherein one of the first plurality of dummy metal features is a dummy via.