Repairable IO in an integrated circuit

• US 8,174,284 B1
• Filed: 01/27/2011
• Issued: 05/08/2012
• Est. Priority Date: 03/03/2010
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Lewis, David
• Primary Examiner(s): LE, DON P
• Application Number:
  US13/014,990
• Time in Patent Office: 467 Days
• Field of Search: 326/9, 326/10, 326 37- 41, 326/46
• US Class Current: 326/10
• CPC Class Codes: H03K 19/17744 for input/output signals
• CPC Class Codes: H03K 19/17764 for reliability

Abstract

Methods and structures for implementing repairable input/output (IO) circuitry in an integrated circuit (IC) are disclosed. One embodiment of the present invention includes repairable IO circuitry along a right, left, or inner column of an IC. Another embodiment includes repairable IO circuitry along a top, bottom, or inner row of an IC. In one embodiment, normal and redundant mode routing is provided between IO buffer circuits and IO register circuits. In another embodiment, normal and redundant mode routing is also provided between IO register circuits and routing to core regions of the IC. One embodiment provides normal and redundant mode routing between two or more IO registers that may span more than one row and/or more than one IO block. One embodiment provides normal and redundant mode routing for different types of IO registers. In some embodiments, redundant mode IO connections shift along with redundant mode connections in a core logic region of the IC. In other embodiments, redundant mode IO connections operate to repair IO circuitry independently of any redundancy scheme in the IC'"'"'s core regions.

Claims

1. An integrated circuit (“

IC”

) comprising;

a plurality of input/output (“

IO”

) buffer circuits;

a plurality of IO register circuits;

normal mode routing including routing operable to couple IO buffer circuits of the plurality of IO buffer circuits to IO register circuits of the plurality of IO register circuits and routing operable to couple IO register circuits of the plurality of IO register circuits to core routing of the IC; and

redundant mode routing including routing operable to couple IO buffer circuits of the plurality of IO buffer circuits to IO register circuits of the plurality of IO register circuits and routing operable to couple IO register circuits of the plurality of IO register circuits to core routing of the IC;

wherein the IC is configurable to utilize either the normal mode routing or the redundant mode routing, the redundant mode routing including at least some routing that is different than the normal mode routing.

2. The IC of claim 1 wherein the plurality of IO register circuits includes a spare IO register circuit and the redundant mode routing includes routing operable to couple an IO buffer circuit of the plurality of IO buffer circuits to the spare IO register circuit and routing operable to couple the spare IO register circuit to core routing of the IC.

3. The IC of claim 1 further including selection circuits configurable to select between the normal mode routing and the redundant mode routing.

4. The IC of claim 1 wherein the IC includes circuitry arranged in rows and the IC is operable to shift rows from a defective row to a spare row and bypass circuitry in the defective row.

5. The IC of claim 1 wherein the normal mode routing further includes routing operable to couple a first IO register circuit to a second IO register circuit and the redundant mode routing includes routing operable to couple the first IO register circuit to a third IO register circuit.

6. An integrated circuit (“

IC”

) comprising;

a plurality of input/output (“

IO”

) register circuits coupled to rows of the IC;

normal mode routing operable to couple two or more IO register circuits of the plurality of IO register circuits that are in different rows of the IC; and

redundant mode routing operable to couple two or more IO register circuits of the plurality of IO register circuits that are in different rows of the IC;

wherein the redundant mode routing is arranged such that the IC is operable in a redundant mode to shift rows from a bypassed row to a spare row and a redundant mode connection between two or more IO register circuits that are in different rows of the IC is operable to replace a normal mode connection between two or more IO register circuits that are in different rows of IC.

7. The IC of claim 6 wherein redundant mode routing is coupled between IO registers in different rows such that alternate redundant mode connections are provided and the alternate redundant mode connections are selectable depending on which IC row is bypassed in a redundant mode.

8. An integrated circuit (“

IC”

) comprising;

a plurality of IO register circuits including register circuits operable to be designated as DQ register circuits and including register circuits operable to be designated as DQS register circuits;

normal mode routing operable to couple the plurality of IO register circuits to row routing of the IC such that designated DQS register circuits are coupled in a normal mode of the IC to some but not all rows of the IC; and

redundant mode routing operable to couple the plurality of IO register circuits to row routing of the IC wherein a row not operable to receive signals from a designated DQS register circuit in a normal mode of the IC is operable to receive signals from the designated DQS register circuit in a redundant mode of the IC.

9. The IC of claim 8 further comprising:

a plurality of IO buffer circuits;

additional normal mode routing operable to couple the plurality of IO buffer circuits to the plurality of IO register circuits;

additional redundant mode routing operable to couple the plurality of IO buffer circuits to the plurality of IO register circuits, the additional redundant mode routing including at least some routing that is different than the additional normal mode routing.

10. The IC of claim 9 wherein:

the additional normal mode routing includes routing operable to couple a first IO buffer circuit to a first designated DQ register circuit and to a first designated DQS register circuit; and

the additional redundant mode routing includes routing operable to couple the first IO buffer circuit to a second designated DQ register circuit and to a second designated DQS register circuit.

11. The IC of claim 8 wherein the IC is operable in a redundant mode to shift rows from a defective row to a spare row to bypass circuitry in the defective row.

12. An integrated circuit (“

IC”

) comprising;

a plurality of IO register circuits;

normal mode routing operable to couple the plurality of IO register circuits to row routing of the IC; and

redundant mode routing operable to couple the plurality of IO register circuits to row routing of the IC;

wherein a pattern of designated types of IO register circuits coupled to row routing of the IC varies from row to row and either the normal mode routing or the redundant mode routing is selectable for operation of the IC and wherein redundant mode routing is operable to couple at least one designated type of IO register circuit to a different row than a row to which the normal mode routing is operable to couple that designated type of IO register circuit.

13. An integrated circuit (“

IC”

) comprising;

a plurality of IO register circuits;

normal mode routing operable to couple the plurality of IO register circuits to row routing of the IC; and

redundant mode routing operable to couple the plurality of IO register circuits to row routing of the IC;

wherein a pattern of designated types of IO register circuits coupled to row routing of the IC varies from row to row and either the normal mode routing or the redundant mode routing is selectable for operation of the IC and wherein the plurality of IO register circuits includes more than one row of spare IO register circuits and the redundant mode routing is operable to couple the IO register circuits to the row routing of the IC such that the IC is configurable to shift connections in a redundant mode by more than one row to maintain the pattern of designated types of IO register circuits from row to row.