Parallel date processing apparatus

• US 8,174,530 B2
• Filed: 06/06/2007
• Issued: 05/08/2012
• Est. Priority Date: 04/09/1999
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Stuttard, Dave, Williams, Dave, O'Dea, Eamon, Faulds, Gordon, Rhoades, John, Cameron, Ken, Atkin, Phil, Winser, Paul, David, Russell, McConnell, Ray, Day, Tim, Greer, Trey
• Primary Examiner(s): Hsu, Joni
• Application Number:
  US11/759,205
• Publication Number:
  US 20080010436A1
• Time in Patent Office: 1,798 Days
• Field of Search: 345/501, 345/502, 345/505, 345/530, 345/559
• US Class Current: 345/505
• CPC Class Codes: G06F 3/14 Digital output to display device ; Cooperation and interconnection of the display device with other functional units
• CPC Class Codes: G09G 2360/121 using a cache memory
• CPC Class Codes: G09G 5/006 Details of the interface to the display terminal specific for a display terminal using a CRT G09G1/167; using a flat panel G09G3/2096; circuits for interfacing with colour displays G09G5/04
• CPC Class Codes: G09G 5/363 Graphics controllers

Abstract

A data processing apparatus includes a plurality of processing elements arranged in a single instruction multiple data array for processing data relating to graphical primitives. Vertex data relating to graphical primitives is used as feedback data for the processing elements for additional processing.

Claims

1. A method of processing data relating to geometrical primitives, each of which has a plurality of vertices, the method using a single instruction multiple data (SIMD) processing apparatus including an array of processing elements, the method comprising the steps of:

assigning data of each different vertex to a different one of the processing elements in the array; and

on each processing element, and in parallel with one another, producing processed vertex data by performing at least one processing step on vertex data assigned to said processing element by said assigning step;

supplying the processed vertex data as feedback data to a mathematical expression evaluator (MEE) through a feedback path,

wherein the MEE is separate from the array of processing elements and evaluates a mathematical expression to produce a data input for each of the processing elements, and

wherein the feedback path includes direct connections to the processing elements and includes a feedback buffer that stores coefficients from the processing elements for the MEE; and

using the feedback path through the feedback buffer and the MEE to communicate data between processing elements, wherein a given data item is communicated as a constant coefficient with other variable coefficients being set to zero.

2. A method as claimed in claim 1, wherein the feedback data are retrieved from a memory store internal to a processing element.

3. A method as claimed in claim 1, wherein the feedback data are retrieved from a register internal to a processing element.

4. A method as claimed in claim 1, wherein the feedback data are buffered before being supplied to the MEE.

5. A method as claimed in claim 1, wherein the feedback data is supplied by one of the processing elements in the array.

6. A method as claimed in claim 1, wherein the feedback data is supplied by a plurality of the processing elements in the array.

7. A method as claimed in claim 1, wherein the array is a SIMD array operable to process a plurality of instruction threads in parallel with one another.

8. A method as claimed in claim 1, wherein the array is arranged in a plurality of SIMD arrays operable to process a plurality of instruction threads in parallel with one another.

9. A method as claimed in claim 1, wherein the at least one processing step is chosen from a group including transformation to screen space, geometry, lighting and shading processing steps.

10. A single instruction multiple data (SIMD) graphical data processing apparatus for processing data relating to geometrical primitives, the apparatus comprising:

an array of processing elements; and

a control device operable to assign data of each different vertex to a different one of the processing elements;

wherein each processing element is operable to produce processed vertex data by performing, in parallel with other processing elements, at least one processing step on vertex data assigned to said processing element by said assignment;

a mathematical expression evaluator (MEE), which is separate from the array of processing elements; and

a feedback bus, wherein the feedback bus is configured to supply the processed vertex data from the array of processing elements to the MEE, wherein the feedback bus includes direct connections to the processing elements and includes a feedback buffer that stores coefficients from the processing elements for the MEE;

wherein the MEE receives the processed vertex data and evaluates a mathematical expression to produce a data input for each of the processing elements; and

wherein the apparatus is configured to use the feedback path through the feedback buffer and the MEE to communicate data between processing elements, wherein a given data item is communicated as a constant coefficient with other variable coefficients being set to zero.

11. An apparatus as claimed in claim 10, wherein the feedback data is retrieved from a memory store internal to a processing element.

12. An apparatus as claimed in claim 10, wherein the feedback data is retrieved from a register internal to a processing element.

13. An apparatus as claimed in claim 10, wherein the control device includes a data buffer operable to buffer the feedback data before that data is supplied to the array.

14. An apparatus as claimed in claim 10, wherein the feedback data is supplied by one of the processing elements.

15. An apparatus as claimed in claim 10, wherein the feedback data is supplied by a plurality of the processing elements.

16. An apparatus as claimed in claim 10, wherein the array is arranged as a plurality of SIMD arrays.

17. An apparatus as claimed in claim 10, wherein the array is a SIMD array, and is operable to process a plurality of instruction threads in parallel with one another.

18. An apparatus as claimed in claim 10, wherein the array is arranged in a plurality of SIMD arrays, the arrays being operable to process a plurality of instruction threads in parallel with one another.

19. An apparatus as claimed in claim 10, comprising direct inter-processing element connections for transfer of processed vertex data therebetween.

20. An apparatus as claimed in claim 10, wherein the at least one processing step is chosen from a group including transformation to screen space, geometry, lighting and shading processing steps.