Efficient readout schemes for analog memory cell devices using multiple read threshold sets

• US 8,174,857 B1
• Filed: 12/30/2009
• Issued: 05/08/2012
• Est. Priority Date: 12/31/2008
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Anobit Technologies, Ltd. (Apple Inc.)
• Inventors: Sommer, Naftali, Perlmutter, Uri
• Primary Examiner(s): Hoang, Huan
• Application Number:
  US12/649,360
• Time in Patent Office: 860 Days
• Field of Search: 365/45, 365/185.03, 365/185.12
• US Class Current: 365/45
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits

Abstract

A method for data readout includes storing two or more candidate sets of read thresholds for reading from a memory device that includes a plurality of analog memory cells. A group of the memory cells from which data is to be read is identified. An order is defined among the candidate sets of the read thresholds responsively to a criterion defined over the group of the memory cells. Data readout from the group of the memory cells is attempted by iterating over the candidate sets according to the order, until the data is read successfully.

Claims

1. A method for data readout, comprising:

storing two or more candidate sets of read thresholds for reading from a memory device that includes a plurality of analog memory cells;

identifying a group of the memory cells from which data is to be read;

defining an order among the candidate sets of the read thresholds responsively to a criterion defined over the group of the memory cells; and

attempting to read data from the group of the memory cells by iterating over the candidate sets according to the order, until the data is read successfully.

2. The method according to claim 1, wherein defining the order comprises causing a first candidate set, which has a first likelihood of reading the data successfully, to appear in the order before a second candidate set, which has a second likelihood, smaller than the first likelihood, of reading the data successfully.

3. The method according to claim 1, wherein the candidate sets comprise at least first and second candidate sets defined respectively for first and second life-cycle stages of the memory cells, and wherein the criterion is defined over a current life-cycle stage of the group of the memory cells.

4. The method according to claim 1, wherein the candidate sets comprise at least first and second candidate sets defined respectively for first and second temperatures of the memory cells, and wherein the criterion is defined over a current temperature of the group of the memory cells.

5. The method according to claim 1, wherein the candidate sets comprise at least first and second candidate sets defined respectively for first and second levels of interference affecting the memory cells, and wherein the criterion is defined over a current interference level affecting the group of the memory cells.

6. The method according to claim 1, wherein the candidate sets comprise at least first and second candidate sets defined respectively for first and second locations of the memory cells in the memory device, and wherein the criterion is defined over a location of the group of the memory cells in the memory device.

7. The method according to claim 1, and comprising:

recording in a data structure an identity of a successful candidate set using which the data was read successfully from the group; and

when preparing to perform subsequent readout from the group, defining the order for performing the subsequent readout responsively to the successful candidate set recorded in the data structure.

8. A data storage apparatus, comprising:

a plurality of analog memory cells; and

circuitry, which is configured to store two or more candidate sets of read thresholds for reading from the analog memory cells, to identify a group of the memory cells from which data is to be read, to define an order among the candidate sets of the read thresholds responsively to a criterion defined over the group of the memory cells, and to attempt to read data from the group of the memory cells by iterating over the candidate sets according to the order, until the data is read successfully.

9. The apparatus according to claim 8, wherein the order causes a first candidate set, which has a first likelihood of reading the data successfully, to appear in the order before a second candidate set, which has a second likelihood, smaller than the first likelihood, of reading the data successfully.

10. The apparatus according to claim 8, wherein the candidate sets comprise at least first and second candidate sets defined respectively for first and second life-cycle stages of the memory cells, and wherein the criterion is defined over a current life-cycle stage of the group of the memory cells.

11. The apparatus according to claim 8, wherein the candidate sets comprise at least first and second candidate sets defined respectively for first and second temperatures of the memory cells, and wherein the criterion is defined over a current temperature of the group of the memory cells.

12. The apparatus according to claim 8, wherein the candidate sets comprise at least first and second candidate sets defined respectively for first and second levels of interference affecting the memory cells, and wherein the criterion is defined over a current interference level affecting the group of the memory cells.

13. The apparatus according to claim 8, wherein the candidate sets comprise at least first and second candidate sets defined respectively for first and second locations of the memory cells in the memory device, and wherein the criterion is defined over a location of the group of the memory cells in the memory device.

14. The apparatus according to claim 8, wherein the circuitry is configured to record in a data structure an identity of a successful candidate set using which the data was read successfully from the group, and, when preparing to perform subsequent readout from the group, to define the order for performing the subsequent readout responsively to the successful candidate set recorded in the data structure.