Semiconductor memory device

• US 8,174,874 B2
• Filed: 09/15/2010
• Issued: 05/08/2012
• Est. Priority Date: 09/18/2009
• Status: Expired due to Fees

• Current Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Inaba, Tsuneo
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): Byrne, Harry W
• Application Number:
  US12/883,019
• Publication Number:
  US 20110069534A1
• Time in Patent Office: 601 Days
• Field of Search: 365/48, 365/55, 365/62, 365/66, 365/74, 365/78, 365 80- 93, 365/100, 365/130, 365/131, 365/148, 365/158, 365171-173, 365/209, 365/213, 365/225.5, 365/230.07, 365/232, 365/243.5, 216/22, 257/295, 257/421, 257/E21.665, 438/3, 428810-816, 428817-8251, 428/826, 977933-935
• US Class Current: 365/158
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect
• CPC Class Codes: G11C 11/1657 Word-line or row circuits
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out
• CPC Class Codes: Y10S 977/935 Spin dependent tunnel, SDT, junction, e.g. tunneling magnetoresistance, TMR

Abstract

According to one embodiment, a semiconductor memory device includes bit line pairs extending in a column direction, each of the bit line pairs includes a first bit line and a second bit line, and memory cell groups connected to the bit line pairs, respectively, and each includes memory cells. Each of the memory cells comprises a first transistor, a second transistor and a resistive memory element. One end of the resistive memory element is connected to the first bit line. A drain region of the first transistor and a drain region of the second transistor are connected to each other and connected to the other end of the resistive memory element. A source region of the first transistor and a source region of the second transistor are connected to the second bit line.

Claims

1. A semiconductor memory device comprising:

bit line pairs extending in a column direction, each of the bit line pairs comprising a first bit line and a second bit line; and

memory cell groups connected to the bit line pairs, respectively, and each comprising memory cells,

wherein each of the memory cells comprises a first transistor, a second transistor and a resistive memory element,

a gate electrode of the first transistor is connected to a first word line extending in a row direction,

a gate electrode of the second transistor is connected to a second word line extending in the row direction,

one end of the resistive memory element is connected to the first bit line,

a drain region of the first transistor and a drain region of the second transistor are connected to each other and connected to the other end of the resistive memory element,

a source region of the first transistor and a source region of the second transistor are connected to the second bit line,

a second transistor of a first memory cell shares a source region with a first transistor of a second memory cell which is adjacent to the first memory cell in the column direction,

two bit line pairs which are adjacent in the row direction comprise a first column unit by connecting first bit lines thereof to each other, or connecting second bit lines thereof to each other,

a second bit line or a first bit line located at a center of the first column unit is formed of a first interconnect layer,

a first bit line or a second bit line located at least one end portion of the first column unit is formed of a second interconnect layer located above the first interconnect layer,

the second interconnect layer is connected to a diffusion region of the first transistor or a diffusion region of the second transistor through a first contact or the resistive memory element, and

a first bit line or a second bit line located at least one end portion is located closer to a center of the first column unit than a connecting part between the bit line and a lower layer.

2. The device of claim 1, wherein first bit lines or second bit lines disposed at both end portions of the first column unit are formed of the second interconnect layer.

3. The device of claim 1, wherein

two first column units adjacent in the row direction comprise a second column unit such that first bit lines or second bit lines formed of the first interconnect layer and located at end portions of the two first column units are connected to each other, and

the first bit lines or the second bit lines located at both end portions of the second column unit are formed of the second interconnect layer.

4. The device of claim 1, further comprising the first column units arranged in the row direction,

wherein a first word line of a first column unit of an odd number is connected to a second word line of a first column unit of an even number.

5. The device of claim 3, further comprising the second column units arranged in the row direction,

wherein a first word line of a second column unit of an odd number is connected to a second word line of a second column unit of an even number.

6. The device of claim 3, wherein the first bit lines or the second bit lines located at both end portions of the second column unit are located above first bit lines or second bit lines, which are adjacent to the bit lines located at both end portions and formed of the first interconnect layer.

7. The device of claim 3, wherein

the first bit lines or the second bit lines connected to each other are formed of a third interconnect layer, and

the third interconnect layer is located below the first interconnect layer.

8. The device of claim 3, wherein the first bit lines or the second bit lines connected to each other are formed of two layers of the first interconnect layer and the second interconnect layer.

9. The device of claim 3, wherein the first bit lines or the second bit lines connected to each other are formed of the second interconnect layer.

10. The device of claim 1, wherein the resistive memory element is a magnetoresistive element.