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Semiconductor memory having electrically floating body transistor

  • US 8,174,886 B2
  • Filed: 09/26/2011
  • Issued: 05/08/2012
  • Est. Priority Date: 11/29/2007
  • Status: Active Grant
First Claim
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1. A semiconductor memory cell comprising:

  • a floating body region configured to be charged to a level indicative of a state of the memory cell;

    a first region in electrical contact with said floating body region;

    a second region in electrical contact with said floating body region and spaced apart from said first region;

    a gate positioned between said first and second regions; and

    a back-bias region configured to inject charge into or extract charge out of said floating body region to maintain said state of the memory cell;

    wherein said state of the memory cell is maintained relatively independent of a voltage applied to said gate.

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