Semiconductor memory having electrically floating body transistor

• US 8,174,886 B2
• Filed: 09/26/2011
• Issued: 05/08/2012
• Est. Priority Date: 11/29/2007
• Status: Active Grant

• Current Assignee: Zeno Semiconductor, Inc.
• Original Assignee: Zeno Semiconductor, Inc.
• Inventors: Widjaja, Yuniarto, Or-Bach, Zvi
• Primary Examiner(s): Nguyen, Tuan T.
• Application Number:
  US13/244,839
• Publication Number:
  US 20120012915A1
• Time in Patent Office: 225 Days
• Field of Search: 365/185.08, 365/63, 365/182, 365/185.03, 365/162
• US Class Current: 365/185.08
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 11/565 using capacitive charge storage elements
• CPC Class Codes: G11C 14/0018 whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor
• CPC Class Codes: G11C 14/0045 and the nonvolatile element is a resistive RAM element, i.e. programmable resistors, e.g. formed of phase change or chalcogenide material
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells
• CPC Class Codes: H10B 41/30 characterised by the memory core region

Abstract

A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; a gate positioned between said first and second regions; and a back-bias region configured to inject charge into or extract charge out of said floating body region to maintain said state of the memory cell. Application of back bias to the back bias region offsets charge leakage out of the floating body and performs a holding operation on the cell. The cell may be a multi-level cell. Arrays of memory cells are disclosed for making a memory device.

Claims

1. A semiconductor memory cell comprising:

a floating body region configured to be charged to a level indicative of a state of the memory cell;

a first region in electrical contact with said floating body region;

a second region in electrical contact with said floating body region and spaced apart from said first region;

a gate positioned between said first and second regions; and

a back-bias region configured to inject charge into or extract charge out of said floating body region to maintain said state of the memory cell;

wherein said state of the memory cell is maintained relatively independent of a voltage applied to said gate.

2. The cell of claim 1, wherein said first region has a first conductivity type selected from a p-type conductivity type and an n-type conductivity type;

said floating body region has a second conductivity type selected from said p-type and n-type conductivity types, said second conductivity type being different from said first conductivity type;

said second region has said first conductivity type; and

said back bias region comprises a substrate having said first conductivity type.

3. The cell of claim 1, further comprising a substrate having a first conductivity type selected from a p-type conductivity type and an n-type conductivity type;

wherein said first region has a second conductivity type selected from said p-type and n-type conductivity types, said second conductivity type being different from said first conductivity type;

wherein said floating body region has said first conductivity type;

wherein said second region has said second conductivity type; and

wherein said back bias region comprises a buried layer having said second conductivity type, said buried layer being positioned between said floating body region and said substrate.

4. The cell of claim 1, further comprising:

a source line terminal electrically connected to one of said first and second regions;

a bit line terminal electrically connected to the other of said first and second regions;

a word line terminal connected to said gate; and

a back bias terminal connected to said back bias region.

5. The cell of claim 2, further comprising:

a source line terminal electrically connected to one of said first and second regions;

a bit line terminal electrically connected to the other of said first and second regions;

a word line terminal connected to said gate; and

a substrate terminal connected to said substrate, said substrate terminal being configured to function as a back bias terminal.

6. The cell of claim 3, further comprising:

a source line terminal electrically connected to one of said first and second regions;

a bit line terminal electrically connected to the other of said first and second regions;

a word line terminal connected to said gate; and

a buried well terminal connected to said buried layer, said buried well terminal being configured to function as a back bias terminal.

7. The cell of claim 4, wherein application of back bias to said back bias terminal offsets charge leakage out of said floating body.

8. The cell of claim 7, wherein said back bias is applied as a constant positive voltage bias.

9. The cell of claim 7, wherein said back bias is applied as a periodic pulse of positive voltage.

10. The cell of claim 1, wherein a maximum potential that can be stored in said floating body is increased by said applying back bias to said back bias region, resulting in a relatively larger memory window.

11. The cell of claim 4, wherein application of back bias to said back bias terminal performs a holding operation on said cell.

12. The cell of claim 1, wherein said cell is a multi-level cell, wherein said floating body is configured to indicate more than one state by storing multi-bits, and wherein said cell is configured for monitoring cell current of said cell to determine a state of said cell.

13. A semiconductor memory array, including:

a plurality of semiconductor memory cells as recited in claim 1 arranged in a matrix of rows and columns.

14. A semiconductor memory array comprising:

a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein each said semiconductor memory cell includes;

a floating body region configured to be charged to a level indicative of a state of the memory cell;

a first region in electrical contact with said floating body region;

a second region in electrical contact with said floating body region and spaced apart from said first region;

a gate positioned between said first and second regions; and

a back-bias region configured to inject charge into or extract charge out of said floating body region to maintain said state of the memory cell, wherein said state of the memory cell is maintained relatively independent of a voltage applied to said gate.

15. The array of claim 14, wherein each said first region has a first conductivity type selected from a p-type conductivity type and an n-type conductivity type;

each said floating body region has a second conductivity type selected from said p-type and n-type conductivity types, said second conductivity type being different from said first conductivity type;

each said second region has said first conductivity type; and

each said back bias region comprises a substrate having said first conductivity type.

16. The array of claim 14, wherein each said cell further comprises a substrate having a first conductivity type selected from a p-type conductivity type and an n-type conductivity type;

wherein each said first region has a second conductivity type selected from said p-type and n-type conductivity types, said second conductivity type being different from said first conductivity type;

wherein each said floating body region has said first conductivity type;

wherein each said second region has said second conductivity type; and

wherein each said back bias region comprises a buried layer having said second conductivity type, said buried layer being positioned between said floating body region and said substrate.

17. The array of claim 14,

wherein each row or column of said cells is connected to a source line terminal electrically connected to each one of said first or second regions of each said cell in said row or column, such that each said row or column is connected by an independently addressable one of said source line terminals;

wherein each of the other of said rows or columns of said cells is connected to a bit line terminal electrically connected to each one of the other of said first or second regions of each said cell in said other of said rows or columns, such that each of said other of said rows or columns is connected by an independently addressable one of said bit line terminals;

wherein each row or column of said cells is connected to a word line terminal electrically connected to each said gate of each said cell in said row or column, such that each said row or column is connected by an independently addressable one of said word line terminals;

wherein at least one row or column of said cells is connected to a back bias terminal electrically connected to each back bias region of each said cell in said at least one row or column.

18. The array of claim 17, wherein said back bias terminal is commonly connected to all of said cells in said array.

19. The array of claim 17, wherein said back bias terminal is segmented to allow independent control of bias applied on a selected portion of said memory array.

20. The array of claim 17, wherein application of back bias to said back bias terminal performs a holding operation on said cells, while a selected cell is accessible via a select one or more of said source line, bit line and word line terminals.

21. The array of claim 17, further comprising voltage generator circuitry configured to apply back bias to said back bias terminal.

22. The array of claim 17, further comprising a reference generator circuit configured to generate an initial cumulative cell current of said memory cells sharing a selected one of said source line being written to.

23. The array of claim 17, further comprising a reference generator circuit configured to generate an initial cumulative cell current of said memory cells sharing a selected one of said source lines being written to.

24. The array of claim 17, further comprising a reference cell configured to stored charge representative of an initial state of said memory cells sharing a selected one of said source lines being written to.

25. The array of claim 14, wherein each said cell is a multi-level cell, wherein each said floating body is configured to indicate more than one state by storing multi-bits.

26. A semiconductor memory cell comprising:

a floating body region configured to be charged to a level indicative of a state of the memory cell;

a first region in electrical contact with said floating body region;

a second region in electrical contact with said floating body region and spaced apart from said first region;

a gate positioned between said first and second regions; and

a back-bias region configured to inject charge into or extract charge out of said floating body region to maintain said state of the memory cell;

wherein said cell is a multi-level cell, and wherein said floating body is configured to indicate more than one state by storing multi-bits.

27. A semiconductor memory array comprising:

a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein each said semiconductor memory cell includes;

a floating body region configured to be charged to a level indicative of a state of the memory cell;

a first region in electrical contact with said floating body region;

a second region in electrical contact with said floating body region and spaced apart from said first region;

a gate positioned between said first and second regions; and

a back-bias region configured to inject charge into or extract charge out of said floating body region to maintain said state of the memory cell;

wherein each said cell is a multi-level cell, wherein each said floating body is configured to indicate more than one state by storing multi-bits.