Multi-standard multi-rate filter

• US 8,176,107 B2
• Filed: 12/15/2006
• Issued: 05/08/2012
• Est. Priority Date: 12/16/2005
• Status: Expired due to Fees

• Current Assignee: CSR Technology Incorporated (Qualcomm, Inc.)
• Original Assignee: CSR Technology Incorporated (Qualcomm, Inc.)
• Inventors: Sturza, Mark Alan, Leimer, Donald
• Primary Examiner(s): Bullock, Jr., Lewis A
• Assistant Examiner(s): Yaary, Michael D
• Application Number:
  US11/611,542
• Publication Number:
  US 20070156800A1
• Time in Patent Office: 1,971 Days
• Field of Search: None
• US Class Current: 708/313
• CPC Class Codes: H03H 17/0277 comprising recursive filters
• CPC Class Codes: H03H 17/0279 having two phases
• CPC Class Codes: H03H 17/0664 where the output-delivery frequency is lower than the input sampling frequency, i.e. decimation

Abstract

A method is provided for decimating a digital signal by a factor of M and matching it to a desired channel bandwidth. The method applies the digital signal input samples to a (M-1) stage tapped delay line, downsamples the input samples and the output samples of each tapped delay line stage by a factor of M, and applies each of the M downsampled sample value streams to M allpass IIR filters, respectively. The M allpass IIR filtered sample streams are then summed and scaled by a factor of 1/M. The result can then be filtered by a digital channel filter.

Claims

1. A quad rate, multi-standard decimation device with decimation ratio selectable from 2, 3, 4, and 6;

and selectable mode, comprising;

a. A first input switch with one branch for decimate by 3, 4, or 6; and

a second branch for decimate by 2;

b. A first digital filter connected to said first input switch decimate by 3,4, or 6 branch;

c. A second switch with input connected to said first digital filter output with one branch for decimate by 4 or 6, and a second branch for decimate by 3;

d. A downsample by 2 connected to said second switch decimate by 4 or 6 branch;

e. A first switching mechanism selecting output of said decimate by 2 or decimate by 3 branch of said second switch depending on which path has been selected;

f. A second switching mechanism selecting output of said first switching mechanism or decimate by 2 branch of said first switch depending on which path has been selected;

g. A third switch connected to the output of said second switching mechanism with one branch for decimate by 3 or 6, and a second branch for decimate by 2 or 4;

h. A combined digital filter, decimate by 3 device connected to said third switch decimate by 3 or 6 output;

i. A combined digital filter, decimate by 2 device connected to said third switch decimate by 2 or 4 output;

j. A third switching mechanism selecting output of said combined digital filter, decimate by 3 device or output of said combined digital filter, decimate by 2 device depending on which path has been selected;

k. A second digital filter connected to output of said third switching mechanism;

l. Said second digital filter bandwidth dependent on selected said mode.

2. The device of claim 1 where said modes include DVB-T/H, ISDB-T, and T-DAB.

3. The device of claim 1 where said first digital filter, said second switch, said downsample by 2, and said first switching mechanism comprise:

a. A first switch connected to the input with one branch for decimate by 3 and a second branch for decimate by 4 or 6;

b. A one sample delay connected to the input;

c. A second switch connected to the output of said one sample delay with one branch for decimate by 3 and a second branch for decimate by 4 or 6;

d. A first downsample by 2 connected to said first switch decimate by 4 or 6 branch;

e. A second downsample by 2 connected to said second switch decimate by 4 or 6 branch;

f. A first switching mechanism selecting said first switch decimate by 3 branch or output of said first downsample by 2 depending on which path has been selected;

g. A second switching mechanism selecting said second switch decimate by 3 branch or output of said second downsample by 2 depending on which path has been selected;

h. A first all pass filter connected to the output of said first switching mechanism;

i. A second all pass filter connected to the output of said second switching mechanism;

j. A summation device adding the outputs of said first allpass filter and of said second allpass filter;

k. A scale by ½

device connected to the output of said summation device.

4. The device of claim 1 where said third switch, said combined digital filter, decimate by 3, said combined filter, decimate by 2, and said third switching mechanism comprise:

a. A first switch connected to the input with one branch for decimate by 2 or 4 and a second branch for decimate by 3 or 6;

b. A first one sample delay connected to the input;

c. A second one sample delay connected to the output of said first one sample delay;

d. A second switch connected to the output of said first one sample delay with one branch for decimate by 2 or 4 and a second branch for decimate by 3 or 6;

e. A first downsample by 2 connected to the decimate by 2 or 4 branch of said first switch;

f. A first downsample by 3 connected to the decimate by 3 or 6 branch of the said first switch;

g. A second downsample by 2 connected to the decimate by 2 or 4 branch of said second switch;

h. A second downsample by 2 connected to the decimate by 3 or 6 branch of said second switch;

i. A first switching mechanism selecting output of said first downsample by 2 or output of said first downsample by 3 depending on which path has been selected;

j. A second switching mechanism selecting output of said second downsample by 2 or output of said second downsample by 3 depending on which path has been selected;

k. A third downsample by 3 connected to the output of said second one sample delay;

mechanism;

l. A first allpass filter connected to output of said first switching mechanism;

m. A second allpass filter connected to the output of said second switching n. A third all pass filter connected to the output of said third downsample by 3;

o. A third switching mechanism selecting zero or selecting the output of said third allpass filter depending on the path selected;

p. A summation device adding the outputs of said first allpass filter, said second all pass filter, and said third switching mechanism;

q. A third switch connected to the output of said summation device with one branch for decimate by 2 or 4 and a second branch for decimate by 3 or 6;

r. A scale by ½

connected to the output of the decimate by 2 or 4 branch of said third switch;

s. A scale by ⅓

connected to the output of the decimate by 3 or 6 branch of said third switch;

t. A fourth switching mechanism selecting the outputs of said scale by ½

or said scale by ⅓

depending on the path selected.

5. The device of claim 1 where said second digital filter device comprises:

a. A first all pass filter connected to the input;

b. A second all pass filter connected to the input;

c. A third allpass filter connected to the output of said second allpass filter;

d. A summation device connected to the outputs of said first allpass filter and of said third allpass filter;

e. A scale by ½

device connected to the output of said summation device.

6. The device of claim 1 where said decimation ratio is selected based on measured ACI.

7. The device claim 1 where said decimation ratio is decreased when measured ACI increases.

8. The device of claim 1 where said decimation ratio is increased when measured ACI decreases.