Non-volatile memories with enhanced write performance and endurance
First Claim
1. A memory system comprising:
- a receiver for receiving a data rate of a data sequence to be written to a non-volatile memory device, the data rate specifying a number of bits in the data sequence;
a physical page selector for;
selecting a physical address of an invalid previously written memory page from a group of physical addresses of invalid previously written memory pages located on the non-volatile memory device, the invalid previously written memory page at the selected physical address having a number of free bits; and
determining if the number of free bits is greater than or equal to the data rate; and
a transmitter for outputting the selected physical address of the invalid previously written memory page in response to the physical page selector determining that the number of free bits is greater than or equal to the data rate.
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Accused Products
Abstract
Enhanced write performance for non-volatile memories including a memory system that includes a receiver for receiving a data rate of a data sequence to be written to a non-volatile flash memory device. The memory system also includes a physical page selector for selecting a physical address of an invalid previously written memory page from a group of physical addresses of invalid previously written memory pages located on the non-volatile memory device, and for determining if the number of free bits in the invalid previously written memory page at the selected physical address is greater than or equal to the data rate. The memory system also includes a transmitter for outputting the selected physical address of the invalid previously written memory page, the outputting in response to the physical page selector determining that the number of free bits is greater than or equal to the data rate.
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Citations
25 Claims
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1. A memory system comprising:
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a receiver for receiving a data rate of a data sequence to be written to a non-volatile memory device, the data rate specifying a number of bits in the data sequence; a physical page selector for; selecting a physical address of an invalid previously written memory page from a group of physical addresses of invalid previously written memory pages located on the non-volatile memory device, the invalid previously written memory page at the selected physical address having a number of free bits; and determining if the number of free bits is greater than or equal to the data rate; and a transmitter for outputting the selected physical address of the invalid previously written memory page in response to the physical page selector determining that the number of free bits is greater than or equal to the data rate. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A computer implemented method for selecting a physical page to write to in a memory system, the method comprising:
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receiving a data rate of a data sequence to be written to a non-volatile memory device, the data rate specifying a number of bits in the data sequence; selecting a physical address of an invalid previously written memory page from a group of physical addresses of invalid previously written memory pages located on the non-volatile memory device, the invalid previously written memory page at the selected physical address having a number of free bits; and determining if the number of free bits is greater than or equal to the data rate; and outputting the selected physical address of the invalid previously written memory page in response to determining that that the number of free bits is greater than or equal to the data rate. - View Dependent Claims (11, 12, 13, 14, 15)
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16. A computer implemented method for erasing memory blocks in a memory system, the method comprising:
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receiving a block erasure request specifying a rewritable not-and (NAND) flash memory device, the rewritable NAND flash memory device comprising one or more memory blocks that are candidates for erasure; selecting a memory block to be erased, the selecting from the one or more memory blocks that are candidates for erasure, the selecting responsive to a number of memory pages containing valid data in a candidate memory block, to a number of free bits in the candidate memory block, and to a number of writes left in the candidate memory block; and initiating an erasure of the selected memory block. - View Dependent Claims (17, 18, 19, 20, 21, 22)
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23. A memory system comprising:
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a receiver for receiving a data sequence to be written to a non-volatile memory device, and for receiving a logical address associated with the data sequence; a physical page selector for selecting a physical page on the non-volatile memory device to be written with the data sequence, the selected physical page having a number of free bits; a multi-write code selector for selecting a write code in response to the number of free bits in the selected physical page and to the data sequence; and a device writer for reading contents of the selected physical page, generating a write sequence that is consistent with the contents of the selected physical page, and writing the write sequence to the selected physical page, the reading, generating and writing performed in response to the selected physical page being a previously written memory page. - View Dependent Claims (24, 25)
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Specification