Command queuing smart storage transfer manager for striping data to raw-NAND flash modules

• US 8,176,238 B2
• Filed: 05/10/2011
• Issued: 05/08/2012
• Est. Priority Date: 12/02/2003
• Status: Expired due to Fees

• Current Assignee: Super Talent Technology, Corporation
• Original Assignee: Super Talent Electronics, Inc.
• Inventors: Yu, Frank, Lee, Charles C., Ma, Abraham C.
• Primary Examiner(s): TSAI, SHENG JEN
• Application Number:
  US13/104,257
• Publication Number:
  US 20110213921A1
• Time in Patent Office: 364 Days
• Field of Search: 711/103, 711/E12.008
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0607 Interleaved addressing
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells

Abstract

A flash module has raw-NAND flash memory chips accessed over a physical-block address (PBA) bus by a NVM controller. The NVM controller is on the flash module or on a system board for a solid-state disk (SSD). The NVM controller converts logical block addresses (LBA) to physical block addresses (PBA). Data striping and interleaving among multiple channels of the flash modules is controlled at a high level by a smart storage transaction manager, while further interleaving and remapping within a channel may be performed by the NVM controllers. A SDRAM buffer is used by a smart storage switch to cache host data before writing to flash memory. A Q-R pointer table stores quotients and remainders of division of the host address. The remainder points to a location of the host data in the SDRAM. A command queue stores Q, R for host commands.

Claims

1. A multi-level flash memory storage system comprising:

a host which uses a downstream interface to a plurality of multi-level flash memory storage subsystems;

a plurality of multi-level flash memory storage subsystems, each multi-level flash memory storage subsystem further comprising;

volatile memory sector buffer means for temporarily storing host data in a volatile memory that loses data when power is disconnected;

a Smart Storage Switch (SSS) which comprises;

an upstream interface to a host for receiving host commands to access Non-Volatile Memory (NVM) and for receiving host data and a host address;

a smart storage transaction manager that manages transactions from the host;

a virtual storage processor that maps the host address to an assigned flash module to generate a Logical Block Address (LBA), the virtual storage processor performing a first level of mapping;

a virtual storage bridge between the smart storage transaction manager and a LBA bus;

a first-level stripping mapper, in the Smart Storage Switch, that maps the LBA to a plurality of flash memory modules;

wherein first-level striping is performed before the host data is sent to flash memory modules;

a plurality of flash memory modules, wherein a flash module in the plurality of flash modules comprises;

a NVM controller, coupled to the LBA bus to receive the LBA generated by the virtual storage processor and to receive the host data from the virtual storage bridge;

a second-level mapper, in the NVM controller, for mapping the LBA to a Physical Block Address (PBA);

a local clock source, within each of the plurality of flash modules, for generating local clocks for clocking the NVM controllers and interfaces to raw-NAND flash memory chips;

wherein local clocks are generated within each of the plurality of flash modules;

raw-NAND flash memory chips, coupled to the NVM controller, for storing the host data at a block location identified by the PBA generated by the second-level mapper in the NVM controller;

wherein a flash memory module is a striping non-volatile-memory (NVM) system which comprises;

a module interface to the virtual storage bridge that generates striping data, address and commands;

wherein the raw-NAND flash memory chips comprise a plurality of NVM devices each having a plurality of NVM memory blocks for storing stripping data that retains data when power is disconnected;

a NVM storage processor that assigns SSS commands to an assigned device in the plurality of NVM devices, the storage processor also storing attributes obtained from each of the plurality of NVM devices, the attributes including memory capacities, wherein the NVM storage processor reports an aggregate sum of the memory capacities to the SSS;

a data striping unit for segmenting SSS data into data segments stored on several of the plurality of NVM devices; and

a storage bridge, coupled between the NVM storage processor and the plurality of NVM devices;

wherein flash memory is arranged as blocks of multiple pages, wherein pages are written and blocks are erased, wherein individual pages are not individually erasable except by erasing all pages in a physical block;

wherein flash memory is further arranged into a plurality of planes that are plane-interleaved and accessible in parallel;

further comprising;

a volatile logical-physical mapping table storing mapping entries, wherein a mapping entry stores a logical address of data from the SSS and a physical block address (PBA) indicating a location of the data within the flash memory;

wherein a mapping entry further comprises a plane number and a page number;

a table restorer for restoring mapping entries in the volatile logical-physical mapping table by accessing blocks of flash memory in a plane-interleaved order,

wherein the volatile logical-physical mapping table is restored from flash memory in the plane-interleaved order using a second least-significant-bit (LSB) as a most-significant bit (MSB) of the physical block address,

whereby address mapping is performed to access the raw-NAND flash memory chips.

2. The multi-level flash memory storage system of claim 1 wherein the plurality of multi-level flash memory storage subsystems are directly soldered to the host on a same circuit board.

3. The multi-level flash memory storage system of claim 1 wherein the plurality of multi-level flash memory storage subsystems are plugged into sockets on the host.

4. The multi-level flash memory storage system of claim 1 wherein the plurality of flash modules plug into flash-module sockets;

wherein the flash-module sockets are mounted to a circuit board;

wherein the circuit board is a motherboard having the host and the multi-level flash memory storage subsystems, or a daughter card having the multi-level flash memory storage subsystems.

5. A flash memory module comprising:

module interface means, coupled to a host, for receiving commands to access flash memory and for receiving data and an address;

a Non-Volatile Memory (NVM) controller, coupled to a LBA bus to receive a LBA from the module interface means;

a local clock source, receiving a clock from the module interface means, for generating local clocks for clocking NVM controllers and interfaces to the flash memory,

data striping mapping means for dividing the data into data segments that are assigned to different ones of a plurality of NVM memory devices;

a plurality of NVM memory devices comprising;

flash memory arranged as blocks of multiple pages, wherein pages are written and blocks are erased, wherein individual pages are not individually erasable except by erasing all pages in a physical block;

wherein the flash memory is further arranged into a plurality of planes that are plane-interleaved and accessible in parallel;

a volatile logical-physical mapping table storing mapping entries, wherein a mapping entry stores a logical address of data from a NVM controller and a physical block address (PBA) indicating a location of the data within the flash memory;

wherein the mapping entries further comprise a plane number and a page number;

a table restorer, coupled to a physical sequential address counter, for restoring mapping entries in the volatile logical-physical mapping table by accessing blocks of the flash memory in a plane-interleaved order determined by the physical sequential address counter,

wherein the volatile logical-physical mapping table is restored from flash memory in a plane-interleaved order using a second least-significant-bit (LSB) as a most-significant bit (MSB) of the physical block address.

6. The flash memory module of claim 5 further comprising a volatile memory buffer means for temporarily storing data in a volatile memory that loses data when power is disconnected.

7. The flash memory module of claim 5 wherein a NVM memory device in the plurality of NVM memory devices comprises a single-chip memory with NVM memories integrated with a controller, and an error-correction code (ECC) processor.

8. The flash memory module of claim 5 wherein the NVM memory device in the plurality of NVM memory devices comprises a single-chip memory with NVM memories integrated with a controller, a striping architecture, and an ECC unit.

9. The flash memory module of claim 5 wherein the NVM memory device in the plurality of NVM memory devices comprises a single-chip memory with NVM memories integrated with an ECC unit.