Shared single-access memory with management of multiple parallel requests
First Claim
1. A processor core comprising:
- a shared memory having a plurality of banks, each bank comprising a plurality of addressable storage locations, wherein addressable storage locations in different banks are accessible in parallel;
a constants memory having a plurality of addressable storage locations, wherein one of the locations at a time is accessible;
a plurality of processing engines adapted to generate a plurality of requests to the shared memory in parallel, each shared memory request specifying a target address in the shared memory and further adapted to generate a plurality of requests to the constants memory in parallel, each constants memory request specifying a target address in the constants memory;
conflict logic coupled between the processing engines and the shared memory, the conflict logic being adapted to receive the plurality of shared memory requests in parallel from the plurality of processing engines, to select a satisfiable set from the received requests, the satisfiable set including requests specifying at most one target address in each of the plurality of banks, and to deliver the satisfiable set of requests in parallel to the shared memory; and
serialization logic coupled between the processing engines and the memory, the serialization logic being adapted to receive the plurality of constants memory requests in parallel from the plurality of processing engines, to select one of the target addresses in the constants memory, and to permit all of the plurality of requests that specify the selected target address in the constants memory to proceed in parallel.
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Abstract
A memory is used by concurrent threads in a multithreaded processor. Any addressable storage location is accessible by any of the concurrent threads, but only one location at a time is accessible. The memory is coupled to parallel processing engines that generate a group of parallel memory access requests, each specifying a target address that might be the same or different for different requests. Serialization logic selects one of the target addresses and determines which of the requests specify the selected target address. All such requests are allowed to proceed in parallel, while other requests are deferred. Deferred requests may be regenerated and processed through the serialization logic so that a group of requests can be satisfied by accessing each different target address in the group exactly once.
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Citations
8 Claims
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1. A processor core comprising:
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a shared memory having a plurality of banks, each bank comprising a plurality of addressable storage locations, wherein addressable storage locations in different banks are accessible in parallel; a constants memory having a plurality of addressable storage locations, wherein one of the locations at a time is accessible; a plurality of processing engines adapted to generate a plurality of requests to the shared memory in parallel, each shared memory request specifying a target address in the shared memory and further adapted to generate a plurality of requests to the constants memory in parallel, each constants memory request specifying a target address in the constants memory; conflict logic coupled between the processing engines and the shared memory, the conflict logic being adapted to receive the plurality of shared memory requests in parallel from the plurality of processing engines, to select a satisfiable set from the received requests, the satisfiable set including requests specifying at most one target address in each of the plurality of banks, and to deliver the satisfiable set of requests in parallel to the shared memory; and serialization logic coupled between the processing engines and the memory, the serialization logic being adapted to receive the plurality of constants memory requests in parallel from the plurality of processing engines, to select one of the target addresses in the constants memory, and to permit all of the plurality of requests that specify the selected target address in the constants memory to proceed in parallel. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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Specification