Shared single-access memory with management of multiple parallel requests

• US 8,176,265 B2
• Filed: 06/21/2011
• Issued: 05/08/2012
• Est. Priority Date: 10/30/2006
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Coon, Brett W., Siu, Ming Y., Xu, Weizhong, Oberman, Stuart F., Nickolls, John R., Mills, Peter C.
• Primary Examiner(s): Rojas, Midys
• Application Number:
  US13/165,638
• Publication Number:
  US 20110252204A1
• Time in Patent Office: 322 Days
• Field of Search: 711/150, 711/151, 711/152, 711/154, 711/158, 711/163, 711/167, 711/168
• US Class Current: 711/150
• CPC Class Codes: G06F 12/084 with a shared cache
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A memory is used by concurrent threads in a multithreaded processor. Any addressable storage location is accessible by any of the concurrent threads, but only one location at a time is accessible. The memory is coupled to parallel processing engines that generate a group of parallel memory access requests, each specifying a target address that might be the same or different for different requests. Serialization logic selects one of the target addresses and determines which of the requests specify the selected target address. All such requests are allowed to proceed in parallel, while other requests are deferred. Deferred requests may be regenerated and processed through the serialization logic so that a group of requests can be satisfied by accessing each different target address in the group exactly once.

Claims

1. A processor core comprising:

a shared memory having a plurality of banks, each bank comprising a plurality of addressable storage locations, wherein addressable storage locations in different banks are accessible in parallel;

a constants memory having a plurality of addressable storage locations, wherein one of the locations at a time is accessible;

a plurality of processing engines adapted to generate a plurality of requests to the shared memory in parallel, each shared memory request specifying a target address in the shared memory and further adapted to generate a plurality of requests to the constants memory in parallel, each constants memory request specifying a target address in the constants memory;

conflict logic coupled between the processing engines and the shared memory, the conflict logic being adapted to receive the plurality of shared memory requests in parallel from the plurality of processing engines, to select a satisfiable set from the received requests, the satisfiable set including requests specifying at most one target address in each of the plurality of banks, and to deliver the satisfiable set of requests in parallel to the shared memory; and

serialization logic coupled between the processing engines and the memory, the serialization logic being adapted to receive the plurality of constants memory requests in parallel from the plurality of processing engines, to select one of the target addresses in the constants memory, and to permit all of the plurality of requests that specify the selected target address in the constants memory to proceed in parallel.

2. The processor core of claim 1 wherein each of the plurality of processing engines is further adapted to generate a request to the shared memory and a request to the constants memory in parallel.

3. The processor core of claim 2 wherein the conflict logic and the serialization logic are further adapted to operate in parallel with each other, and wherein the shared memory and the constants memory are further adapted to operate in parallel with each other.

4. The processor core of claim 1 wherein the serialization logic includes:

a broadcast selection module adapted to select one of the target addresses from the plurality of requests as a broadcast address and to assert a broadcast signal corresponding to each request for which the target address matches the broadcast address; and

decision logic coupled to the broadcast selection module and adapted to assert or deassert a go signal for each request based at least in part on the broadcast signal.

5. The processor core of claim 4 wherein the conflict logic includes:

a conflict detection module adapted to assert a conflict signal corresponding to each request of the plurality of requests that conflicts with another request of the plurality of requests; and

decision logic coupled to the conflict detection module and adapted to determine, based at least in part on the conflict signals, which of the requests to include in the satisfiable set.

6. The processor core of claim 5 wherein the conflict logic further includes:

a broadcast selection module adapted to select one of the target addresses from the plurality of requests as a broadcast address and to assert a broadcast signal corresponding to each request for which the target address matches the broadcast address,

wherein the decision logic is further adapted to include in the satisfiable set any request whose target address matches the broadcast address regardless of whether the conflict signal corresponding to that request is asserted.

7. The processor core of claim 1 wherein the processing engines have read access and write access to the shared memory and further have only read access to the constants memory.

8. The processor core of claim 1 wherein the constants memory is a cache memory.