Programmable microcontroller architecture

• US 8,176,296 B2
• Filed: 10/22/2001
• Issued: 05/08/2012
• Est. Priority Date: 10/26/2000
• Status: Active Grant

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Snyder, Warren
• Primary Examiner(s): Alrobaye, Idriss N
• Application Number:
  US10/033,027
• Publication Number:
  US 20020108006A1
• Time in Patent Office: 3,851 Days
• Field of Search: 712/15, 712/17, 712/18, 712/35, 712/36, 712/37, 712/38, 712/32, 716/13, 716/14, 716/17
• US Class Current: 712/32
• CPC Class Codes: G05B 19/0423 Input/output
• CPC Class Codes: G05B 2219/25033 structure, control, syncronization, data, alarm, connect I-O line to interface
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 1/32 Means for saving power
• CPC Class Codes: G06F 13/102 where the programme performs an interfacing function, e.g. device driver G06F13/105 takes precedence; scheduling within device drivers G06F9/52; contention policies within device drivers G06F9/4881
• CPC Class Codes: G06F 13/36 for access to common bus or bus system
• CPC Class Codes: G06F 13/40 Bus structure for computer networks G06F15/163; for optical bus networks H04B10/25
• CPC Class Codes: G06F 13/4068 Electrical coupling
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G06F 15/7817 Specially adapted for signal processing, e.g. Harvard architectures
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: G06F 9/44505 Configuring for program initiating, e.g. using registry, configuration files
• CPC Class Codes: G06G 7/06 Programming arrangements, e.g. plugboard for interconnecting functional units of the computer; Digital programming hybrid computers G06J
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: H03B 5/32 being a piezoelectric resonator selection of piezoelectric material H10N30/00
• CPC Class Codes: H03B 5/364 the amplifier comprising field effect transistors H03B5/366 takes precedence
• CPC Class Codes: H03H 19/004 Switched capacitor networks
• CPC Class Codes: H03K 3/012 Modifications of generator to improve response time or to decrease power consumption
• CPC Class Codes: H03K 3/014 Modifications of generator to ensure starting of oscillations
• CPC Class Codes: H03K 3/02315 Stabilisation of output, e.g. using crystal

Abstract

Embodiments of the present invention are directed to a microcontroller device having a microprocessor, programmable memory components, and programmable analog and digital blocks. The programmable analog and digital blocks are configurable based on programming information stored in the memory components. Programmable interconnect logic, also programmable from the memory components, is used to couple the programmable analog and digital blocks as needed. The advanced microcontroller design also includes programmable input/output blocks for coupling selected signals to external pins. The memory components also include user programs that the embedded microprocessor executes. These programs may include instructions for programming the digital and analog blocks “on-the-fly,” e.g., dynamically. In one implementation, there are a plurality of programmable digital blocks and a plurality of programmable analog blocks.

Claims

1. A microprocessor circuit, comprising:

a plurality of programmable analog circuit blocks wherein said analog circuit blocks are dynamically programmable and configurable to perform one or more of a plurality of various analog function and wherein said plurality of programmable analog circuit blocks comprises a matrix of n by m, n and m independently being an integer of at least two;

each of said plurality of programmable analog circuit blocks is configured to provide one or more analog function and wherein said plurality of programmable analog circuit blocks are configured to be individually at different power levels;

a plurality of programmable digital circuit blocks configured to provide at least one of a plurality of digital functions, wherein each programmable digital circuit block is configurable to perform any one of said digital functions upon being configured with a single register write operation;

a routing matrix configured to couple a subset of said plurality of programmable analog circuit blocks to a first subset of said plurality of programmable digital circuit blocks, at least a first one of said programmable analog circuit blocks being coupled to at least a first one of said programmable digital circuit blocks; and

a programmable non-volatile memory coupled directly or indirectly to said plurality of programmable digital circuit blocks and said plurality of programmable analog circuit blocks, said programmable memory comprising data for programming at least one of said programmable digital circuit blocks and at least one of said plurality of programmable analog circuit blocks.

2. The circuit as recited in claim 1, wherein when programmed, each of said plurality of programmable analog circuit blocks provides at least one of said plurality of analog functions.

3. The circuit of as recited in claim 1, wherein when programmed, each programmable digital circuit blocks provides at least one of said digital functions.

4. The circuit as recited in claim 2, wherein when programmed, said plurality of programmable analog circuit blocks and said plurality of programmable digital circuit blocks provides at least one digital and/or analog function.

5. The circuit as recited in claim 1, wherein when programmed, said routing matrix couples a second one of said subset of said plurality of programmable analog circuit blocks to a second one of said subset of said plurality of programmable digital circuit blocks.

6. The circuit as recited in claim 1, wherein each of said plurality of programmable analog circuit blocks is configured to provide one or more analog functions selected from the group consisting of a gain function, a comparator function, a switched capacitor function, a filter function, an analog to digital conversion function, a digital to analog conversion function, and an amplifier function.

7. The circuit as recited in claim 1, wherein at least two of said plurality of programmable digital circuit blocks are coupled in series to provide a digital system function.

8. A microcontroller means, comprising:

a plurality of programmable analog means wherein said analog means are dynamically programmable and configurable to perform one or more of a plurality of various analog functions and wherein said plurality of programmable analog means comprises a matrix of n by m, n and m independently being an integer of at least two;

each of said plurality of programmable analog means is configured to provide one or more analog functions and wherein said plurality of programmable analog means are configured to be individually at different power levels;

a plurality of programmable digital means configured to provide at least one of a plurality of digital means, wherein each programmable digital means is configured to perform any one of said digital function upon being configured with a single register write operation;

a routing means configured to couple a subset of said plurality of programmable analog means to a first subset of said plurality of programmable digital means, at least a first one of said programmable analog means being coupled to at least a first one of said programmable digital means; and

a programmable non-volatile memory means coupled directly or indirectly to said plurality of programmable digital means and said plurality of programmable analog means, said programmable memory means comprising data for programming at least one of said programmable digital means and at least one of said plurality of programmable analog means.

9. The microcontroller means as recited in claim 8, wherein when programmed, each of said plurality of programmable analog means provides at least one of said plurality of analog function.

10. The microcontroller means as recited in claim 8, wherein when programmed, each programmable digital means provides at least one of said digital function.

11. The microcontroller means as recited in claim 8, wherein when programmed, said plurality of programmable analog means and said plurality of programmable digital means provideds at least one digital and/or analog function.

12. The microcontroller means as recited in claim 8, wherein when programmed, said routing means couples a second one of said subset of said plurality of programmable analog means to a second one of said subset of said plurality of programmable digital means.

13. The circuit as recited in claim 8, wherein each of said programmable analog means is configured to provide one or more analog means selected from the group consisting of a gain means, a comparator means, a switched capacitor means, a filter means, an analog to digital conversion means, a digital to analog conversion means, and an amplifier means.

14. The circuit as recited in claim 8, wherein at least two of said plurality of programmable digital means are coupled in series to provide a digital system function.

15. A microcontroller circuit, comprising:

a microprocessor;

a plurality of programmable analog circuit blocks wherein said programmable analog circuit blocks are dynamically programmable and configurable to perform one or more of a plurality of various analog functions and wherein said plurality of programmable analog circuit blocks comprises a matrix of n, by m, n and m independently being an integer of at least two;

each of said plurality of programmable analog circuit blocks is configured to provide one or more analog function and wherein said plurality of programmable analog circuit blocks are configured to be individually at different power levels;

a plurality of programmable digital circuit blocks configured to provide at least one of a plurality of digital functions, wherein each programmable digital circuit block is configurable to perform any one of said digital functions upon being configured with a single register write operation;

a routing matrix configured to couple a subset of said plurality of programmable analog circuit blocks to a first subset of said plurality of programmable digital circuit blocks, at least a first one of said programmable analog circuit blocks being coupled to at least a first one of said programmable digital circuit blocks; and

a programmable non-volatile memory coupled directly or indirectly to said plurality of programmable digital circuit blocks and said plurality of programmable analog circuit blocks, said programmable memory comprising data for programming at least one of said programmable digital circuit blocks and at least one of said plurality of programmable analog circuit blocks.

16. The circuit as recited in claim 15, wherein when programmed, each of said plurality of programmable analog circuit blocks provides at least one of said plurality of analog functions.

17. The circuit as recited in claim 15, wherein when programmed, each programmable digital circuit block provides at least one of said digital functions.

18. The circuit as recited in claim 15, wherein when programmed, said plurality of programmable analog circuit blocks and said plurality of programmable digital circuit blocks provides at least one digital and/or analog function.

19. The circuit as recited in claim 15, wherein when programmed, said routing matrix couples a second one of said subset of said plurality of programmable analog circuit blocks to a second one of said subset of said plurality of programmable digital circuit blocks.

20. The circuit as recited in claim 15, wherein each of said plurality of programmable analog circuit blocks is configured to provide one or more analog functions selected from the group consisting of a gain function, a comparator function, a switched capacitor function, a filter function, an analog to digital conversion function, a digital to analog conversion function, and an amplifier function.

21. The circuit as recited in claim 15, wherein at least two of said plurality of programmable digital circuit blocks are coupled in series to provide a digital system function.