Method and apparatus for addressing actual or predicted failures in a FLASH-based storage system

• US 8,176,360 B2
• Filed: 09/05/2009
• Issued: 05/08/2012
• Est. Priority Date: 08/11/2009
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: Texas Memory Systems Incorporated (International Business Machines Corporation)
• Inventors: Frost, Holloway H., Fuxa, James A., Camp, Charles J.
• Primary Examiner(s): Lohn, Joshua
• Application Number:
  US12/554,888
• Publication Number:
  US 20110040925A1
• Time in Patent Office: 976 Days
• Field of Search: 714/6, 714/7, 714/755, 714/766, 714/776, 714/6.24, 714/6.3, 714/6.32, 711/114, 711/103
• US Class Current: 714/6.24
• CPC Class Codes: G06F 11/1016 Error in accessing a memory location, i.e. addressing error
• CPC Class Codes: G06F 11/1044 with specific ECC/EDC distribution
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 11/1076 Parity data used in redundant arrays of independent storages, e.g. in RAID systems
• CPC Class Codes: G06F 11/108 Parity data distribution in semiconductor storages, e.g. in SSD
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/14 Protection against unauthorised use of memory or access to memory
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0644 Management of space entities, e.g. partitions, extents, pools
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents

Abstract

Methods and apparatuses for enhanced protection of data stored in a FLASH memory system involve a controller capable of adapting to the failure of one or more FLASH memory devices in the memory system. The controller stores data in the form of page stripes, each page stripe composed of data pages, and each data page stored in a different FLASH memory device. The controller also detects failure of a FLASH memory device in which a data page of a particular page stripe is stored, reconstructs the data page, and stores the reconstructed data page in a new page stripe, where the number of data pages in the new page stripe is less than the number of data pages in the particular page stripe, and where no page of the new page stripe is stored in a memory location within the failed FLASH memory device.

Claims

1. A FLASH memory based solid state storage system capable of adapting to the failure of one or more FLASH memory chips comprising:

a printed circuit board;

a plurality of FLASH memory chips mounted to the printed circuit board, each FLASH memory chip including a plurality of FLASH memory cells arranged to store a plurality of pages of digital data and a chip-level communications bus interface capable of receiving and sending digital data to be stored in, and retrieved from, FLASH memory cells within the FLASH memory chip; and

a system controller including a plurality of system communication bus interfaces, each system communication bus interface being coupled by a system communications bus to one or more chip-level communication bus interfaces such that the system controller can provide digital data to and retrieve digital data from memory cells within the one or more FLASH memory chips, the system controller further including an external communications bus interface capable of receiving digital data to be stored within the storage system;

wherein the system controller is configured to store data received over the external communications bus in the plurality of FLASH memory chips in the form of page stripes, each page stripe comprising a plurality of pages of data stored in the FLASH memory chips, each of the plurality of pages being stored in a FLASH memory chip that is different from each of the FLASH memory chips in which the other pages of data within the page stripe are stored, the plurality of pages making up the page stripe including a plurality of data pages, each data page storing data initially received over the external communications bus, and further including at least one data protection page containing data that may be used to reconstruct data stored in a data page within the page stripe that becomes corrupted or unavailable; and

wherein the system controller is further configured to;

detect the failure of at least a portion of a FLASH memory chip in which a data page of a particular page stripe is stored;

reconstruct data that was stored within a data page of the particular page stripe using data in the data protection page for the particular page stripe; and

store the reconstructed data page as a data page within a new page stripe, wherein the number of data pages within the new page stripe is less than the number of data pages that were in the particular page stripe, and wherein no page of the new page stripe is stored in a memory location within the failed portion of the FLASH memory chip, such that each FLASH memory chip used by the system controller for a given page stripe stores either a page of data or data that may be used to reconstruct data stored in a data page for that given page stripe.

2. The FLASH memory based solid state storage system of claim 1 wherein each system communications bus couples the system controller to two FLASH memory chips.

3. The FLASH memory based solid state storage system of claim 1 wherein the system controller is mounted to the same printed circuit board as the plurality of FLASH memory chips.

4. The FLASH memory based solid state storage system of claim 1 further comprising circuitry for generating the data protection information for each page stripe by performing XOR operations on data from the data pages within the page stripe.

5. The FLASH memory based solid state storage system of claim 1 wherein the system controller is configured such that the data protection information for a first page stripe can be written to FLASH memory using a system communication bus that is different from the system communication bus used to write the data protection information for a second page stripe to FLASH memory.

6. The FLASH memory based solid state storage system of claim 1 wherein the system is configured such that each data page includes error correction code data generated using the data within the page that was initially received over the external communication bus.

7. The FLASH memory based solid state storage system of claim 1 wherein each FLASH memory chip has the same physical construction and includes a number of planes with each plane constituting a collection of memory cells arranged into a collection of pages of memory and associated circuitry that allows for intra-plane movement of data from one page location within the plane into another page location within the plane;

and where the system controller is configured such that, for each of a majority of the page stripes, the pages of data that make up the page stripe are all stored within the same plane of the respective FLASH chips in which the page stripe is stored.

8. A board-mounted FLASH-based memory storage system comprising:

a printed circuit board;

a plurality of FLASH memory devices, each mounted to the printed circuit board;

a controller mounted to the printed circuit board; and

a plurality of communications buses, each configured to allow the controller to write a data collection to one or more FLASH memory devices;

wherein the controller is configured to write data to the FLASH memory devices in a striped fashion using data stripes, where each data stripe includes a group of data collections and an associated set of data protection information such that

(a) each data collection within a group of data collections is written into a FLASH memory device that differs from (i) the FLASH memory devices into which the other data collections within the group of data collections are written and (ii) the FLASH memory device to which the data protection information associated with the group of data collections is written;

(b) the communications bus used to write each data collection into a FLASH memory device differs from the communication buses used to write the other data collections within the group of data collections into their respective FLASH memory devices; and

(c) the number of data collections used to form each data stripe is based, at least in part, on failure information associated with the FLASH memory devices such that the controller can adjust the number of data collections used for one or more data stripes in response to information indicating that all or part of one or more FLASH memory devices has failed, and such that each FLASH memory device used by the controller for a given data stripe contains either a data collection or a set of data protection information for that given data stripe stored in a physical memory location within the FLASH memory device.

9. The board-mounted FLASH-based memory storage system of claim 8 where each of the FLASH memory devices is a single level cell NAND FLASH memory device.

10. The board-mounted FLASH-based memory storage system of claim 8 wherein each data collection corresponds to the maximum amount of data that can be written to a specific physical memory location within a FLASH memory device during one WRITE operation.

11. The board-mounted FLASH-based memory storage system of claim 8 wherein the controller is configured to respond to failure information associated with one or more portions of a FLASH memory device by:

(i) no longer using the one or more portions associated with the failure information for the storage of data collections but (ii) continuing to use other portions of the FLASH memory device for the storage of data collections.

12. The board-mounted FLASH-based memory storage system of claim 11 wherein the controller is further configured such that, upon the failure of only a portion of a FLASH memory device, the FLASH memory device may be used to store data collections from a data stripe having N data collections and to store data collections from a data stripe having M data collections, where M and N are integers and where M and N are different.

13. The board-mounted FLASH-based memory storage system of claim 11 wherein the controller is configured such that, in the absence of failure information indicating the failure of a FLASH memory device, the number of data collections used to form each data stripe is one less than the number of communication buses.

14. The board-mounted FLASH based memory storage system of claim 8 wherein the failure information reflects a predicted failure of a portion of a FLASH memory device.

15. A memory system comprising:

a plurality of FLASH memory chips, each of the plurality of FLASH memory chips being associated with a plurality of physical memory address locations;

a system controller that includes an external communication bus interface for receiving WRITE requests from an external host device, wherein each WRITE request includes a data item and a logical memory address associated with the data item, the system controller further comprising a plurality of internal communication bus interfaces, each allowing the system controller to write data into physical memory locations associated with one or more of the FLASH memory chips; and

a plurality of internal data communication buses, each internal data communication bus coupling one or more of the FLASH memory chips to an internal communication bus interface of the system controller;

wherein the system controller is configured, for each WRITE request, to translate the logical memory address provided by the external host to a physical memory address and to write the data item provided as part of the WRITE request to the physical memory location corresponding to the physical memory address; and

wherein the system controller is further configured to;

(i) associate a number of data items received through a plurality of WRITE requests with each other to form a group of received data items;

(ii) generate data protection information for each group and write the data protection information to a physical memory location;

(iii) perform the translation of the received logical addresses for the data items in the group and select the physical memory location for storage of the data protection information such that each of the data items is stored in a physical memory location within a FLASH memory chip that is different from the FLASH memory chips in which the other data items and the data protection information for the group of received data items are stored; and

(iv) adjust the number of data items used to form each group in response to information indicating the actual or predicted failure of all or part of one or more FLASH memory chips, such that the number of data items in one group of received data items stored during a time when all of the FLASH memory chips are operable can differ from the number of data items in a second group of received data items stored at a time after the predicted or actual failure of all or part of one or more FLASH memory chips, and such that each physical memory location addressed by the system controller for a given group of received data items stores either a data item associated with the given group of received data items or data protection information for the given group of received data items.

16. The memory system of claim 15 wherein the system controller is configured to receive WRITE requests directly from the external host device.

17. The memory system of claim 15 wherein the system controller is configured to receive logical memory addresses within a range defining a logical address space;

wherein the plurality of FLASH memory devices define physical memory locations defining a physical address space; and

wherein the total number of logical memory addresses within the logical address space is less than the total number of physical memory locations within the physical address space.

18. The memory system of claim 15 wherein the number of data items for all groups of received data items is less than ten.

19. The memory system of claim 15 wherein the system controller is configured such that, upon failure of a part of a FLASH memory chip, the remaining portions of the FLASH memory chip continue to be used for the storage of data such that the same FLASH memory chip can be used to store data items from a first group of N data items and data items from a second group of M data items, where N and M are integers and wherein N and M are different.

20. The memory system of claim 15 further including a printed circuit board and wherein the FLASH memory chips, system controller and internal data communication buses are mounted on the printed circuit board.