Systems and methods for managing end of life in a solid state drive

• US 8,176,367 B2
• Filed: 05/28/2009
• Issued: 05/08/2012
• Est. Priority Date: 05/28/2009
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Agere Systems Incorporated (Broadcom, Inc.)
• Inventors: Dreifus, David L., Warren, Robert W., McKean, Brian
• Primary Examiner(s): Beausoliel, Jr., Robert
• Assistant Examiner(s): Mehrmanesh, Elmira
• Application Number:
  US12/473,454
• Publication Number:
  US 20100306577A1
• Time in Patent Office: 1,076 Days
• Field of Search: 714 61- 32, 714/47, 714/47.1, 714/47.2, 714/47.3, 714/54
• US Class Current: 714/47.3
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 29/76 using address translation or modifications

Abstract

Various embodiments of the present invention provide systems and methods for managing solid state drives. As an example, a storage system is described that include at least a first flash memory block and a second flash memory block, and a control circuit. The first flash memory block and the second flash memory block are addressable in the storage system. The control circuit is operable to identify the first flash memory block as partially failed, receive a write request directed to the first flash memory block; and direct the write request to the second flash memory block.

Claims

1. A solid state drive, the solid state drive comprising:

a first number of memory portions each including a plurality of flash memory cells, wherein a second number of the first number of memory portions are addressable, and wherein a difference between the first number and the second number is an over provisioned number of memory portions;

a control circuit, wherein the controller circuit includes;

an unreliable block identification circuit, wherein the unreliable block identification circuit is operable to determine that one or more of the first number of memory portions is unreliable, and wherein upon determining that one or more of the first number of memory portions is unreliable the over provisioned number of memory portions is reduced; and

a partial failure indication circuit, wherein the partial failure indication circuit is operable to disallow write access to any of the memory portions upon determination that the over provisioned number of memory portions is less than or equal to a threshold level;

a time stamp circuit, wherein the time stamp circuit is operable to identify a first point in time when the partial failure indication circuit disallowed write access to the memory portions; and

an end of life indication circuit, wherein the end of life indication circuit is operable to estimate a second point in time when the ability to read one or more of the plurality of memory portions can no longer be guaranteed by adding a fixed time increment to the point in time, wherein the fixed time increment is a predefined estimate of how long data will remain readable in the memory cells after the first point in time.

2. A storage device, the storage device comprising:

a plurality of flash memory cells;

an unreliable block identification circuit operable to determine that a subset of the flash memory cells is unreliable;

a partial failure indication circuit, wherein the partial failure indication circuit is operable to disallow write access to the subset of the flash memory cells determined as unreliable;

a time stamp circuit operable to identify a first point in time when the partial failure indication circuit disallowed write access to the subset of the flash memory cells of the flash memory cells; and

an end of life indication circuit, wherein the end of life indication circuit is operable to estimate a second point in time based at least in part on the first point in time, wherein the second point in time indicates when the ability to read one or more of the plurality of memory portions can no longer be guaranteed.

3. The storage device of claim 2, wherein the storage device is deployed as part of a solid state drive.

4. The storage device of claim 2, wherein the time stamp circuit includes:

a timer circuit that provides the point in time.

5. The storage device of claim 2, wherein the storage device is communicably coupled to a host, and wherein the point in time is provided by the host to the time stamp circuit.

6. The storage device of claim 2, wherein the end of life indication circuit adds a fixed time increment to the first point in time.

7. The storage device of claim 6, wherein the fixed time increment is a predefined estimate of how long data will remain readable in the plurality of memory cells after the determination that an insufficient number of the plurality of memory portions remain reliable.

8. A storage system, the storage system comprising:

a first non-volatile memory portion and a second non-volatile memory portion, wherein the first non-volatile memory portion and the second non-volatile memory portion are addressable in the storage system;

an unreliable block identification circuit, wherein the unreliable block identification circuit is operable to determine that the first non-volatile memory portion is unreliable;

a failure indication circuit, wherein the failure indication circuit is operable to identify the first non-volatile memory portion as read only upon determination that a subset of the first non-volatile memory portion that is unreliable exceeds a threshold level;

a time stamp circuit operable to identify a first point in time when the failure indication circuit identified the first non-volatile memory portion as read only; and

an end of life indication circuit operable to estimate a second point in time based at least in part on the first point in time, wherein the second point in time is an estimated end of life of the first solid state drive.

9. The storage system of claim 8, wherein the first non-volatile memory portion, the second non-volatile memory portion, and the control circuit are implemented in a single non-volatile memory device.

10. The storage system of claim 8, wherein the storage system further comprises:

a control circuit operable to receive a write request directed to the first non-volatile memory portion, and direct the write request to the second non-volatile memory portion based at least in part on identification of the first non-volatile memory portion as read only.

11. The storage system of claim 10, wherein the control circuit is further operable to:

receive a read request directed to the first non-volatile memory portion; and

direct the read request to the first non-volatile memory where the read request is received prior to directing the write request to the second non-volatile memory.

12. The storage system of claim 10, wherein the first non-volatile memory portion is included in a first solid state drive, wherein the second non-volatile memory portion is included in a second solid state drive, and wherein the control circuit is included in a system controller that is communicably coupled to the first solid state drive and the second solid state drive.

13. The storage system of claim 12, wherein the control circuit receives a write prohibit signal from the first solid state drive, and wherein identifying the first non-volatile memory portion as partially failed is based at least in part on the write prohibit signal, and includes identifying the first solid state drive as partially failed.

14. The storage system of claim 13, wherein the control circuit is a first control circuit, wherein the first solid state drive includes a second control circuit, and wherein the second control circuit includes:

an unreliable block identification circuit, wherein the unreliable block identification circuit is operable to determine that the first non-volatile memory portion is unreliable; and

a partial failure indication circuit, wherein the partial failure indication circuit is operable to assert the write prohibit signal upon determination that an insufficient number of memory portions in the first solid state drive remain reliable.

15. The storage system of claim 10, wherein the control circuit is implemented in a system control unit, wherein the system control unit includes a plurality of interfaces, wherein a first replaceable memory device includes the first non-volatile memory portion and is installed in a first of the plurality of interfaces, and wherein a second replaceable memory device includes the second non-volatile memory portion and is installed in a second of the plurality of interfaces.

16. The storage system of claim 15, wherein the plurality of interfaces are selected from a group consisting of:

USB interfaces, DIMM interfaces, and a combination of DIMM interfaces and USB interfaces.

17. The storage system of claim 8, wherein the first non-volatile memory portion is included in a first solid state drive, wherein the second non-volatile memory portion is included in a second solid state drive, wherein the storage system further comprises:

a system controller communicably coupled to the first solid state drive and the second solid state drive, wherein the end of life circuit is included in the system controller.

18. The storage system of claim 17, wherein the system controller is operable to assure that all data from the first solid state drive is transferred to the second solid state drive before the estimated end of life.