Apparatus and method for performing cyclic redundancy check (CRC) on partial protocol data units (PDUs)

• US 8,176,385 B2
• Filed: 05/21/2009
• Issued: 05/08/2012
• Est. Priority Date: 10/26/2004
• Status: Expired due to Fees

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Brocade Communications Systems, Inc. (Broadcom, Inc.)
• Inventors: Uzrad-Nali, Oran, Plotz, Kevin G., Leichty, Phil L
• Primary Examiner(s): Alphonse, Fritz
• Application Number:
  US12/470,450
• Publication Number:
  US 20100077284A1
• Time in Patent Office: 1,083 Days
• Field of Search: 714/758, 714/781, 714/801
• US Class Current: 714/758
• CPC Class Codes: H04L 49/90 Buffering arrangements

Abstract

The present invention discloses an apparatus and method for performing cyclic redundancy check (CRC) on partial protocol data units (PDUs). The disclosed apparatus is designed to off-load the CRC calculation for transmit or receive from a host computer. According to the disclosed method, when generating CRC for partial PDUs, for each such PDUs a decision is made to determine whether a CRC action is required, i.e., if CRC should be calculated, checked or placed in the outgoing byte stream. When partial CRC calculation is performed the intermediate value is saved into memory and later is used for calculating the CRC for a consecutive partial PDU. In accordance with a preferred embodiment of the invention, the need to re-calculate the CRC in a case of a re-transmit request is eliminated.

Claims

1. An apparatus for processing protocol data units (PDUs), comprising:

a cyclic redundancy check (CRC) controller;

a direct memory access (DMA) controller coupled to the CRC controller; and

a memory coupled to the CRC controller and the DMA controller, the memory storing a plurality of partial inbound PDUs;

wherein the DMA controller transfers each of the plurality of inbound partial PDUs to the memory as each of the plurality of inbound PDUs is received; and

wherein the CRC controller calculates a first intermediate CRC value for a first inbound partial PDU, and further calculates one or more subsequent intermediate CRC values for each of the plurality of partial inbound PDUs remaining, as each of the plurality of inbound PDUs is received.

2. The apparatus of claim 1, wherein the first intermediate CRC value is based upon an initial CRC value, and the one or more subsequent intermediate CRC values are each based upon an intermediate CRC value calculated for a previously processed inbound partial PDU.

3. The apparatus of claim 1, further comprising:

a plurality of processing nodes each coupled to the CRC controller and the DMA controller, the plurality of processing nodes comprising a first processing node associated with the inbound PDU, and further comprising a second processing node associated with a second inbound PDU comprising a second plurality of inbound partial PDUs;

wherein a first CRC channel is associated with the inbound PDU, and a second CRC channel is associated with the second inbound PDU; and

wherein the first and second CRC channels together enable the DMA controller to interact with both the first and second processing nodes, and further together enable the CRC controller to pipeline partial CRC calculations for each of the first and second PDUs.

4. The apparatus of claim 1,

wherein if a current inbound intermediate CRC value is associated with a partial inbound PDU of the plurality of partial inbound PDUs that is at the end of the inbound PDU, the DMA controller compares the current inbound intermediate CRC value to a received CRC value within the inbound PDU;

and

wherein an error is signaled by the DMA controller to the CRC controller if the current inbound intermediate CRC value does not match the received CRC value.

5. The apparatus of claim 1, wherein the inbound PDU comprises an Internet Small Computer System Interface (iSCSI) PDU.

6. A method for processing protocol data units (PDUs), comprising:

a direct memory access (DMA) controller storing a plurality of partial inbound PDUs as each of the plurality of inbound PDUs is received, an inbound PDU comprising the plurality of partial inbound PDUs; and

a cyclic redundancy check (CRC) controller calculating a first intermediate CRC value for a first inbound partial PDU, and further calculating one or more subsequent intermediate CRC values for each of the plurality of partial inbound PDUs remaining, as each of the plurality of partial inbound PDUs is received.

7. The method of claim 6, wherein the first intermediate CRC value is based upon an initial CRC value, and the one or more subsequent CRC values are each based upon an intermediate CRC value calculated for a previously processed inbound partial PDU.

8. The method of claim 6, further comprising:

the DMA controller comparing a current inbound intermediate CRC value to a received CRC value included within the inbound PDU, the current inbound intermediate CRC value associated with a partial inbound PDU of the plurality of partial inbound PDUs that is received at the end of the inbound PDU; and

the DMA controller signaling an error to the CRC controller if the current inbound intermediate CRC value does not match the received CRC value.

9. The method of claim 6, further comprising:

a first processing node associating a first of a plurality of CRC channels with the inbound PDU;

a second processing node associating a second of the plurality of CRC channels with a second inbound PDU; and

the first and second processing nodes communicating with the DMA controller and pipelining partial CRC calculations for both the first and second CRC channels.