Power-aware debugging

• US 8,176,453 B2
• Filed: 09/11/2009
• Issued: 05/08/2012
• Est. Priority Date: 01/23/2009
• Status: Active Grant

• Current Assignee: Synopsys Incorporated
• Original Assignee: Springsoft USA Incorporated (Synopsys Incorporated)
• Inventors: Yang, Kai, Liu, Tayung, Tsai, Furshing, Hsu, Chih Neng, Ang, Ting Shih, Zhao, Jun
• Primary Examiner(s): LIN, SUN J
• Application Number:
  US12/558,259
• Publication Number:
  US 20100192115A1
• Time in Patent Office: 970 Days
• Field of Search: 716/56, 716/104, 716/106, 716/109, 716/110, 716/112, 716/127, 716/133
• US Class Current: 716/106
• CPC Class Codes: G06F 2119/06 Power analysis or power optimisation
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

A debugging system produces displays in response to an IC design and results of a logic simulation of IC behavior based on the IC design. The IC design includes a hardware description language (HDL) model of the IC describing the IC as comprising cell instances communicating via data signals and power sources for supplying power to the cell instances. The IC design also includes power definition markup language (PDML) model describing a power intent of the IC design. The debugging system generates displays representing HDL code that are annotated to indicate how the power intent of the IC design described by the PDML model relates to the portion of the HDL model represented by the display. The debugging system also generates signals trace displays indicating how both the logic and power intent of the IC design affect the value of a user-selected signal at a user-selected time during the logic simulation.

Claims

1. A computer-readable storage device containing software which, when executed by a computer, causes the computer to carry out a method of processing an integrated circuit (IC) design and results of a logic simulation of a behavior of a simulated version of an IC based on the IC design, wherein the IC design includes a hardware description language (HDL) model of the IC describing the IC as comprising a plurality of cell instances communicating via data signals and power sources for supplying power to the cell instances, and a power definition markup language (PDML) model describing a power intent of the IC design, the method comprising steps of:

a. responding to a user input by generating a display representing a portion of the HDL model of the IC, and

b. augmenting the display to indicate how the power intent of the IC design described by the PDML model relates to the portion of the HDL model represented by the display.

2. The computer-readable storage device in accordance with claim 1

wherein the display depicts a portion of HDL code of the HDL model and includes code referencing data signals whose values during the logic simulation are influenced by the power intent described by the PDML model, and

wherein step b comprises annotating the portion of the HDL code depicted in the display that references a data signal having a value influenced by the power intent to indicate how the value of the data signal is influenced by the power intent described by the PDML model.

3. The computer-readable storage device in accordance with claim 2

wherein the HDL code depicted in the display includes a reference to a data signal that the PDML model indicates is subject to level-shifting, and

wherein the reference to that data signal is annotated at step b to indicate that the data signal is subject to level-shifting.

4. The computer-readable storage device in accordance with claim 2

wherein the user input indicates a particular simulation time during the logic simulation,

wherein the HDL code depicted in the display includes a reference to a data signal that the PDML model indicates is subject to retention by a retention cell instance, and

wherein the reference to that data signal is annotated at step b to indicate that the data signal is subject to retention and to indicate whether that data signal was saved or restored by the retention cell instance at the particular simulation time.

5. The computer-readable storage device in accordance with claim 2

wherein the user input selects a particular simulation time during the logic simulation,

wherein the HDL code depicted in the display includes a reference to a data signal that the PDML model indicates is subject to isolation by an isolation cell instance, and

wherein the reference to that data signal is annotated at step b to indicate that the data signal is subject to isolation and to indicate whether that data signal was isolated by the isolation cell instance at the particular simulation time.

6. The computer-readable storage device in accordance with claim 1

wherein the user input selects a particular simulation time during the logic simulation,

wherein the PDML model indicates at least one of the power sources can be turned on and off during IC operation,

wherein the display includes representations of cell instances forming the represented portion of the IC and the power sources that supply power to the cell instances represented, including a representation of at least one of the power sources that can be turned on or off during IC operation, and

wherein each representation of the power source that can be turned on or off during IC operation is annotated at step b to indicate whether it was on or off at the particular simulation time.

7. The computer-readable storage device in accordance with claim 1

wherein the user input selects a particular simulation time during the logic simulation,

wherein the PDML model indicates at least one of the power sources has an output voltage that can vary during IC operation,

wherein the display includes representations of cell instances forming the represented portion of the IC and the power sources that supply power to the the cell instances represented, including a representation of at least one of the power sources has an output voltage that can vary during IC operation, and

wherein each representation of a power source having an output voltage that can vary during IC operation is annotated at step b to indicate a magnitude of the output voltage at the particular simulation time.

8. The computer-readable storage device in accordance with claim 1

wherein the user input selects a particular data signal of the IC and selects a particular simulation time during the logic simulation;

wherein step a comprises responding to the user input by processing the HDL model to determine a particular portion of the IC that generated the particular data signal,

wherein the display generated at step a comprises a trace display including representations of cell instances included within the particular portion of the IC, representations of data signals transmitted and received by the cell instances represented in the trace display, a representation of each power source supplying power signals to any cell instance represented in the trace display, and representations of the power signals, and

wherein the representations of data signals and the representations of the power signals in the trace display are annotated to indicate their values at the particular simulation time.

9. The computer-readable storage device in accordance with claim 8

wherein the PDML model describes at least one power source represented in the trace display as capable of being turned on and off during IC operation, and

wherein the representation of the at least one power source in the trace display is annotated at step b to indicate whether the at least one power source was on or off at the particular simulation time.

10. The computer-readable storage device in accordance with claim 9

wherein the particular data signal has an unknown value at the particular simulation time, and

wherein an automatic trace operation is performed at step a to determine which cell instances could have caused the particular data signal to have the unknown value at the particular simulation time, thereby to determine which cell instances are to be represented in the display.

11. The computer-readable storage device in accordance with claim 10

wherein the display identifies a representation of a power signal that was turned off at the particular simulation time input as being a cause of the particular data signal having an unknown value at the particular simulation time.

12. The computer-readable storage device in accordance with claim 8

wherein the PDML model describes at least one power source represented in the trace display as being able to produce a power signal having a voltage that can vary in magnitude during IC operation, and

wherein the display is annotated at step b to indicate the magnitude of the voltage of the power signal at the particular simulation time.

13. The computer-readable storage device in accordance with claim 8

wherein the PDML describes at least one data signal represented in the trace display as being subject to retention by a retention cell instance,

wherein the trace display includes a representation of the retention cell instance as receiving the at least one of the data signal and as receiving a control signal for selecting a mode of operation of the retention cell instance, and

wherein the trace display is annotated at step b to indicate the mode of operation of the retention cell instance at the particular simulation time.

14. The computer-readable storage device in accordance with claim 8

wherein the PDML describes at least one of the data signals as being subject to isolation by an isolation cell instance,

wherein the trace display includes a representation of the isolation cell instance as receiving the at least one data signal and as receiving a control signal for selecting a mode of operation of the isolation cell instance, and

wherein the trace display is annotated at step b to indicate the mode of operation of the isolation cell instance at the particular simulation time.

15. The computer-readable storage device in accordance with claim 14

wherein the trace display also represents the isolation cell instance as atse receiving a clamp signal for controlling a voltage of an output signal of the isolation cell instance when the isolation cell instance is operating in an isolating mode of operation, and

wherein the display is annotated at step b to indicate a voltage of the clamp signal at the particular simulation time.

16. The computer-readable storage device in accordance with claim 8

wherein the trace display visually distinguishes displayed representations of data signals for which a change in data signal value would affect a value of the particular data signal at the particular simulation time from displayed representations of other data signals, and

wherein the trace display visually distinguishes displayed representations of power signals for which a change in on or off state would affect a value of the particular data signal at the particular simulation time from displayed representations of other power signals.

17. The computer-readable storage device in accordance with claim 8

wherein an automatic trace operation is performed at step a to determine which cell instances affect state of the particular data signal at the particular simulation time, thereby to determine which cell instances are to be represented in the display.

18. The computer-readable storage device in accordance with claim 17

wherein the PDML model describes at least one of the data signals as being subject to isolation,

wherein one of the cell instances in the display is an isolation cell instance depicted as receiving a clamp signal input having an unknown voltage magnitude at the particular simulation time, and

wherein the display identifies the clamp signal input as being a cause of the particular data signal having an unknown value at the particular simulation time.

19. The computer-readable storage device in accordance with claim 1

wherein the PDML model describes a set of legal power intent states of the IC,

wherein the display lists the legal power intent states described by the PDML model,

wherein the display indicates in which one of the legal power intent states, if any, the results of the logic simulation indicate the simulated version of the IC operated at the particular simulation time, and

wherein the display provides a warning if the results of the logic simulation indicate the simulated version of the IC was operating in an illegal power intent state at the particular simulation time.