Metalorganic chemical vapor deposition (MOCVD) growth of high performance non-polar III-nitride optical devices

• US 8,178,373 B2
• Filed: 10/28/2010
• Issued: 05/15/2012
• Est. Priority Date: 12/11/2006
• Status: Active Grant

• Current Assignee: National Institute of Advanced Industrial Science and Technology (Government of Japan), Regents of the University of California (University of California)
• Original Assignee: Japan Science & Technology Trading Co. Limited, Regents of the University of California (University of California)
• Inventors: Schmidt, Mathew C., Kim, Kwang Choong, Sato, Hitsohi, DenBaars, Steven P., Speck, James S., Nakamura, Shuji
• Primary Examiner(s): Smith, Zandra
• Assistant Examiner(s): JOY, JEREMY J
• Application Number:
  US12/914,906
• Publication Number:
  US 20110037052A1
• Time in Patent Office: 565 Days
• Field of Search: 257/E21.001, 257/E33.01, 257102-103, 438/29, 438/46
• US Class Current: 438/29
• CPC Class Codes: B82Y 20/00 Nanooptics, e.g. quantum optics or photonic crystals
• CPC Class Codes: H01L 21/0237 Materials
• CPC Class Codes: H01L 21/02389 Nitrides
• CPC Class Codes: H01L 21/02458 Nitrides
• CPC Class Codes: H01L 21/02507 Alternating layers, e.g. superlattice
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 33/0075 comprising nitride compounds
• CPC Class Codes: H01S 2304/04 MOCVD or MOVPE
• CPC Class Codes: H01S 5/34333 with a well layer based on Ga(In)N or Ga(In)P, e.g. blue laser

Abstract

A method of device growth and p-contact processing that produces improved performance for non-polar III-nitride light emitting diodes and laser diodes. Key components using a low defect density substrate or template, thick quantum wells, a low temperature p-type III-nitride growth technique, and a transparent conducting oxide for the electrodes.

Claims

1. A method for fabricating a non-polar III-nitride optoelectronic device, comprising:

(a) growing a non-polar n-type III-nitride layer on a non-polar III-nitride substrate or template;

(b) growing a non-polar active region including a non-polar quantum well structure on or above the non-polar n-type III-nitride layer, wherein a non-polar quantum well in the non-polar quantum well structure emits light having a peak output power for a thickness of the non-polar quantum well greater than 8 nanometers;

(c) growing a non-polar p-type III-nitride layer on or above the non-polar active region; and

(d) wherein the non-polar III-nitride optoelectronic device has an external quantum efficiency (EQE) of at least 35%, and an output power of at least 25 mW at a drive current of 20 mA.

2. The method of claim 1, wherein the non-polar III-nitride substrate or template is a bulk non-polar III-nitride substrate or template grown by an ammonothermal method or by hydride vapor phase epitaxy (HVPE).

3. The method of claim 1, wherein the non-polar III-nitride substrate or template is a non-polar sidewall lateral epitaxial overgrowth (SLEO) substrate or template grown by metalorganic chemical vapor deposition (MOCVD) or by hydride vapor phase epitaxy (HVPE).

4. The method of claim 1, wherein non-polar quantum well structure is grown at temperatures ranging from approximately 845°

C. to 890°

C.

5. The method of claim 1, wherein quantum barriers in the non-polar quantum well structure are grown to be approximately 10 to 18 nanometers thick.

6. The method of claim 1, wherein quantum barriers in the non-polar quantum well structure are grown at temperatures ranging from approximately 915°

C. to 940°

C.

7. The method of claim 1, wherein the non-polar p-type III-nitride layer is grown at a temperature less than 150°

C. more than a quantum well growth temperature.

8. The method of claim 1, wherein the non-polar p-type III-nitride layer is grown at a quantum barrier growth temperature.

9. The method of claim 1, further comprising depositing transparent oxide electrodes on the device.

10. The method of claim 9, wherein the electrodes are comprised of indium-tin-oxide (ITO) or zinc oxide (ZnO).

11. An optoelectronic device fabricated using the method of claim 1.

23. The method of claim 1, wherein the non-polar quantum well is grown to be approximately 8 to 12 nanometers thick.

12. A method for fabricating a non-polar III-nitride optoelectronic device, comprising:

(a) growing an n-type III-nitride layer on a non-polar III-nitride substrate or template;

(b) growing an active region including a quantum well structure on or above the n-type III-nitride layer;

(c) growing a non-polar p-type III-nitride layer on or above the active region; and

(d) wherein the non-polar III-nitride optoelectronic device has an external quantum efficiency (EQE) of at least 35%, and an output power of at least 25 mW at a drive current of 20 mA.

13. The method of claim 12, wherein a non-polar quantum well in the non-polar quantum well structure is grown to be approximately 8 to 12 nanometers thick.

14. The method of claim 12, wherein the non-polar III-nitride substrate or template is a bulk non-polar III-nitride substrate or template grown by an ammonothermal method or by hydride vapor phase epitaxy (HVPE).

15. The method of claim 12, wherein the non-polar III-nitride substrate or template is a non-polar sidewall lateral epitaxial overgrowth (SLEO) substrate or template grown by metalorganic chemical vapor deposition (MOCVD) or by hydride vapor phase epitaxy (HVPE).

16. The method of claim 12, wherein non-polar quantum well structure is grown at temperatures ranging from approximately 845°

C. to 890°

C.

17. The method of claim 12, wherein quantum barriers in the non-polar quantum well structure are grown to be approximately 10 to 18 nanometers thick.

18. The method of claim 12, wherein quantum barriers in the non-polar quantum well structure are grown at temperatures ranging from approximately 915°

C. to 940°

C.

19. The method of claim 12, wherein the non-polar p-type III-nitride layer is grown at a temperature less than 150°

C. more than a quantum well growth temperature.

20. The method of claim 12, wherein the non-polar p-type III-nitride layer is grown at a quantum barrier growth temperature.

21. The method of claim 12, further comprising depositing transparent oxide electrodes on the device.

22. The method of claim 21, wherein the electrodes are comprised of indium-tin-oxide (ITO) or zinc oxide (ZnO).