High performance system-on-chip inductor using post passivation process

• US 8,178,435 B2
• Filed: 05/27/2003
• Issued: 05/15/2012
• Est. Priority Date: 12/21/1998
• Status: Expired due to Term

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lin, Mou-Shiung
• Primary Examiner(s): MITCHELL, JAMES M
• Application Number:
  US10/445,558
• Publication Number:
  US 20030222295A1
• Time in Patent Office: 3,276 Days
• Field of Search: 438622-626
• US Class Current: 438/622
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05 of an individual bonding area
• CPC Class Codes: H01L 2224/13022 the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 23/3192 Multilayer coating
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/5222 Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/5228 Resistive arrangements or effects of, or between, wiring layers other resistive arrangements H01L23/647
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 23/60 Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 23/642 Capacitive arrangements H01L23/49589, H01L23/645, H01L23/647, H01L23/66 take precedence; capacitive effects between wiring layers on the semiconductor body H01L23/5222
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 23/647 Resistive arrangements H01L23/66, H01L23/62 take precedence
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 27/0676 comprising combinations of diodes, or capacitors or resistors
• CPC Class Codes: H01L 27/08 including only semiconductor components of a single kind
• CPC Class Codes: H01L 28/10 : Inductors
• CPC Class Codes: H01L 28/20 : Resistors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01011 : Sodium [Na]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01038 : Strontium [Sr]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1423 : Monolithic Microwave Integrated Circuit [MMIC]
• CPC Class Codes: H01L 2924/19015 : including thin film passive components
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/19104 : on the semiconductor or solid-state device, i.e. passive-on-chip
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

A system and method for forming post passivation inductors, and related structures, is described. High quality electrical components, such as inductors and transformers, are formed on a layer of passivation, or on a thick layer of polymer over a passivation layer.

Claims

1. A method of forming a post passivation system, comprising:

providing a silicon substrate, a first interconnect metal layer over said silicon substrate, a second interconnect metal layer over said first interconnect metal layer, a dielectric layer between said first and second interconnect metal layers, a first metal pad over said silicon substrate, and a passivation layer over said first and second interconnect metal layers, wherein said passivation layer comprises a nitride layer, wherein a first opening in said passivation layer is over a first contact point of said first metal pad and has a width greater than 0.1 micrometers, and said first contact point is at a bottom of said first opening, wherein said passivation layer has a top surface with a first region and a second region, wherein said first opening is between said first and second regions;

forming a first polymer layer on said passivation layer, wherein a second opening in said first polymer layer exposes said first opening and said first and second regions, wherein said forming said first polymer layer comprises exposing and developing said first polymer layer;

forming a patterned circuit layer over said first polymer layer, on said first and second regions and on said first contact point, wherein said patterned circuit layer comprises a coil over said first polymer layer, wherein said coil is connected to said first contact point through said first and second openings, wherein said forming said patterned circuit layer comprises forming a glue layer, next forming a seed layer over said glue layer, next forming a bulk metal layer over said seed layer, and then removing said seed layer and said glue layer not under said bulk metal layer; and

forming a second polymer layer over said patterned circuit layer.

2. The method of claim 1, wherein said first polymer layer comprises polyimide.

3. The method of claim 1, wherein said second polymer layer comprises polyimide.

4. The method of claim 1, wherein said passivation layer further comprises an oxide layer.

5. The method of claim 1, wherein said patterned circuit layer completely covers entire sidewalls of said second opening.

6. The method of claim 1, wherein said patterned circuit layer covers only a part of sidewalls of said second opening.

7. The method of claim 1, wherein said first polymer layer comprises benzocyclobutene (BCB).

8. The method of claim 1, wherein said forming said first polymer layer comprises spin coating.

9. The method of claim 1, wherein said forming said first polymer layer comprises screen printing.

10. The method of claim 1, wherein said forming said first polymer layer comprises laminating a dry film.

11. The method of claim 1, wherein said forming said glue layer comprises forming a titanium-containing layer, said forming said seed layer comprises forming a gold seed layer on said titanium-containing layer, and said forming said bulk metal layer comprises electroplating a bulk gold layer on said gold seed layer.

12. The method of claim 1, wherein said forming said glue layer comprises sputtering a titanium-containing layer to a thickness between 500 and 5000 Angstroms.

13. The method of claim 1, wherein said forming said seed layer comprises sputtering a gold seed layer to a thickness between 300 and 3000 Angstroms on said glue layer.

14. The method of claim 1, wherein said forming said bulk metal layer comprises electroplating a bulk gold layer to a thickness between 1 and 20 micrometers on said seed layer.

15. The method of claim 1, wherein said forming said seed layer comprises forming a copper seed layer on said glue layer, and said forming said bulk metal layer comprises electroplating a bulk copper layer on said copper seed layer.

16. The method of claim 1, wherein said forming said glue layer comprises sputtering a titanium-containing layer to a thickness between 200 and 1500 Angstroms.

17. The method of claim 1, wherein said forming said seed layer comprises sputtering a copper seed layer to a thickness between 2000 and 10,000 Angstroms on said glue layer.

18. The method of claim 1, wherein said forming said bulk metal layer comprises electroplating a bulk copper layer to a thickness between 2 and 20 micrometers on said seed layer.

19. The method of claim 15, wherein said forming said patterned circuit layer further comprises forming a nickel layer over said bulk copper layer.

20. The method of claim 19, wherein said forming said patterned circuit layer comprises said forming said nickel layer to a thickness between 0.1 and 3 micrometers.

21. The method of claim 1 further comprising providing a second metal pad over said silicon substrate, wherein a third opening in said passivation layer is over a second contact point of said second metal pad, and said second contact point is at a bottom of said third opening, wherein a fourth opening in said first polymer layer is over said second contact point, wherein said coil has a first terminal connected to said first contact point through said first and second openings and a second terminal connected to said second contact point through said third and fourth openings.

22. The method of claim 1, wherein said coil has a first terminal connected to said first contact point through said first and second openings and a second terminal configured for external connection.

23. The method of claim 22, wherein said patterned circuit layer further comprises a wire bond pad connected to said second terminal, wherein a third opening in said second polymer layer is over a second contact point of said wire bond pad, and said second contact point is at a bottom of said third opening.

24. The method of claim 1 further comprising forming a conductive plate over said passivation layer, followed by said forming said first polymer layer further on said conductive plate, followed by said forming said patterned circuit layer with said coil further vertically over said conductive plate.

25. The method of claim 24, wherein said conductive plate is connected to said coil.

26. The method of claim 24, wherein said conductive plate is left electrically floating.

27. The method of claim 24, wherein said conductive plate is connected to a voltage level.

28. The method of claim 1 further comprising providing a transistor in or on said silicon substrate.

29. The method of claim 1 further comprising said forming said first polymer layer with a thickness between 2 and 150 micrometers.

30. The method of claim 1, wherein said second opening has only one sidewall, wherein said patterned circuit layer completely covers said sidewall of said second opening.

31. The method of claim 1, wherein said second opening has only one sidewall, wherein said patterned circuit layer covers only a part of said sidewall of said second opening.

32. The method of claim 1, wherein said forming said patterned circuit layer further comprises forming a photoresist layer over said seed layer, wherein a third opening in said photoresist layer exposes a third region of said seed layer, followed by said forming said bulk metal layer over said third region, followed by removing said photoresist layer, followed by said removing said seed layer and said glue layer not under said bulk metal layer.

33. The method of claim 22 further comprising forming a solder connected to said second terminal.

34. The method of claim 23 further comprising wirebonding to said wire bond pad.

35. The method of claim 1, wherein said second opening has a sidewall slope greater than 45 degrees.

36. The method of claim 1, wherein said second opening has a sidewall slope between 50 and 60 degrees.

37. The method of claim 1, after said forming said second polymer layer, further comprising forming a third opening in said second polymer layer.