Method and configuration for connecting test structures or line arrays for monitoring integrated circuit manufacturing

• US 8,178,876 B2
• Filed: 04/30/2004
• Issued: 05/15/2012
• Est. Priority Date: 10/15/2003
• Status: Active Grant

• Current Assignee: PDF Solutions
• Original Assignee: PDF Solutions
• Inventors: Hess, Christopher, Goldman, David
• Primary Examiner(s): LE, DUNG ANH
• Application Number:
  US10/595,384
• Publication Number:
  US 20090037131A1
• Time in Patent Office: 2,937 Days
• Field of Search: 257/48, 438/11, 438/14, 438/15, 438/18, 716 51- 52, 716/56
• US Class Current: 257/48
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

A test chip comprises at least one level having an array of regions. Each region is capable of including at least one test structure. At least some of the regions include respective test structures. The level has a plurality of driver lines that provide input signals to the test structures. The level has a plurality of receiver lines that receive output signals from the test structures. The level has a plurality of devices for controlling current flow. Each test structure is connected to at least one of the driver lines with a first one of the devices in between. Each test structure is connected to at least one of the receiver lines with a second one of the devices in between, so that each of the test structures can be individually addressed for testing using the driver lines and receiver lines.

Claims

1. A test chip, comprising:

at least one level having an m×

n array of regions, where m and n are integers, each region capable of including at least one test structure, at least some of the regions including respective test structures,

the level having m+1 driver lines oriented in a first direction, the m+1 driver lines connected to collectively provide input signals to all of the test structures,

the level having 4n receiver lines arranged in a second direction, the 4n receiver lines connected to collectively receive output signals from all of the test structures,

wherein the test structures are arranged and connected so that each of the structures can be individually addressed for testing using the m+1 driver lines and 4n receiver lines.

2. The test chip of claim 1, wherein:

each test structure is connected to at least one of the driver lines with a first diode, transistor or controlled switch therebetween, and

each test structure is connected to at least one of the receiver lines with a second diode, transistor or controlled switch therebetween.

3. The test chip of claim 1, wherein:

each test structure has two inputs connected by respective diodes, transistors or controlled switches to a respective two of the driver lines, and

each test structure has two outputs connected by respective diodes, transistors or controlled switches to a respective two of the receiver lines.

4. The test chip of claim 1, wherein:

the test structures are arranged in m columns and n rows,

each column has a first one of the driver lines adjacent thereto and connected thereto on a first side thereof and a second one of the driver lines adjacent thereto and connected thereto on a second side thereof,

each row has a first pair of the receiver lines adjacent thereto and connected thereto on a first side thereof and a second pair of the receiver lines adjacent thereto and connected thereto on a second side thereof.

5. The test chip of claim 1, wherein:

the test structures are arranged in n columns and m rows,

each row has a first one of the driver lines adjacent thereto and connected thereto on a first side thereof and a second one of the driver lines adjacent thereto and connected thereto on a second side thereof,

each column has a first pair of the receiver lines adjacent thereto and connected thereto on a first side thereof and a second pair of the receiver lines adjacent thereto and connected thereto on a second side thereof.

6. The test chip of claim 1, wherein:

the test chip has p levels with test structures, where p is an integer greater than one, each of the p levels having m×

n regions, at least some of the regions in each level containing test structures,

the chip has p×

(m+1) driver lines, with each test structure connected to a respective at least one of the driver lines,

the chip has 8n receiver lines, with each test structure connected to a respective at least one of the receiver lines,

wherein the test structures are arranged and connected so that each of the p×

(m×

n) test structures can be individually addressed for testing using the p×

(m+1) driver lines and 8n receiver lines.

7. The test chip of claim 6, wherein:

the p levels include odd numbered levels and even numbered levels,

each level has 4n receiver lines,

the respective commonly positioned receiver lines from each of the odd numbered levels are connected to each other, and

the respective commonly positioned receiver lines from each of the even numbered levels are connected to each other.

8. The test chip of claim 1, wherein each test structure has four or fewer pins.

9. A test chip, comprising:

at least one level having an array of regions, each region capable of including at least one test structure, at least some of the regions including respective test structures,

the level having a plurality of driver lines that provide input signals to the test structures,

the level having a plurality of receiver lines that receive output signals from the test structures,

the level having a plurality of devices for controlling current flow,

wherein each test structure is connected to at least one of the driver lines with a first one of the devices therebetween, and

each test structure is connected to at least one of the receiver lines with a second one of the devices therebetween, so that each of the test structures can be individually addressed for testing using the driver lines and receiver lines.

10. The test chip of claim 9, wherein:

each test structure has two inputs connected by respective devices to a respective two of the driver lines, and the devices are from the group consisting of diodes, transistors and controlled switches, and

each test structure has two outputs connected by respective devices to a respective two of the receiver lines, and the devices are from the group consisting of diodes, transistors and controlled switches.

11. The test chip of claim 9, wherein:

the test structures are arranged in m columns and n rows,

each column has a first one of the driver lines adjacent thereto and connected thereto on a first side thereof and a second one of the driver lines adjacent thereto and connected thereto on a second side thereof,

each row has a first pair of the receiver lines adjacent thereto and connected thereto on a first side thereof and a second pair of the receiver lines adjacent thereto and connected thereto on a second side thereof.

12. The test chip of claim 9, wherein:

the test structures are arranged in n columns and m rows,

each row has a first one of the driver lines adjacent thereto and connected thereto on a first side thereof and a second one of the driver lines adjacent thereto and connected thereto on a second side thereof,

each column has a first pair of the receiver lines adjacent thereto and connected thereto on a first side thereof and a second pair of the receiver lines adjacent thereto and connected thereto on a second side thereof.

13. The test chip of claim 9, wherein:

the test chip has p levels with test structures, where p is an integer greater than one, each of the p levels having regions, at least some of the regions in each level containing test structures, the p levels include odd numbered levels and even numbered levels,

each level has commonly positioned receiver lines,

the respective commonly positioned receiver lines from each of the odd numbered levels are connected to each other, and

the respective commonly positioned receiver lines from each of the even numbered levels are connected to each other.

14. The test chip of claim 9, wherein each test structure has four or fewer pins.

15. A test chip, comprising:

at least one level having an array of regions with m columns and n rows, where m and n are integers, each region capable of including at least one test structure, at least some of the regions including respective test structures,

the level having m+1 driver lines oriented in a first direction, with the m columns arranged between successive ones of the m+1 driver lines, each test structure having two inputs connected by respective diodes, transistors, or controlled switches to a respective two of the driver lines, the m+1 driver lines collectively providing input signals to all of the test structures,

the level having 4n receiver lines oriented in a second direction, each of the n rows arranged between a respective first pair of the 4n receiver lines on a first side thereof and a respective second pair of the 4n receiver lines on a second side thereof, each test structure having first and second outputs connected by respective diodes, transistors or controlled switches to respective ones of the receiver lines on the first and second side of that test structure, so that the 4n receiver lines collectively receive output signals from all of the test structures, whereby each of the structures can be individually addressed for testing.

16. The test chip of claim 15, wherein:

the test chip has p levels with test structures, where p is an integer greater than one, each of the p levels having m×

n regions, at least some of the regions in each level containing test structures,

the chip has p×

(m+1) driver lines, with each test structure connected to a respective at least one of the driver lines,

the chip has 8n receiver lines, with each test structure connected to a respective at least one of the receiver lines,

wherein the test structures are arranged and connected so that each of the p×

(m×

n) test structures can be individually addressed for testing using the p×

(m+1) driver lines and 8n receiver lines.

17. The test chip of claim 16, wherein:

the p levels include odd numbered levels and even numbered levels,

each level has 4n receiver lines,

the respective commonly positioned receiver lines from each of the odd numbered levels are connected to each other, and

the respective commonly positioned receiver lines from each of the even numbered levels are connected to each other.

18. The test chip of claim 15, wherein each test structure has four or fewer pins.

19. A test chip, comprising:

at least one layer having n regions, where n an integer, each region capable of including at least one test structure, at least some of the regions including respective test structures, each comprising a nest of m parallel lines, where m is an integer,

the at least one layer having m driver lines, the m driver lines connected to provide input signals to the respective m parallel lines in each nest,

the at least one layer having at least 2n receiver lines, the at least 2n receiver lines connected to collectively receive output signals from all of the test structures,

wherein the test structures are arranged and connected to the m driver lines and at least 2n receiver lines so that a presence of a short or open circuit defect in any of the nests can be identified.

20. The test chip of claim 19, wherein the layer has 3n receiver lines.

21. The test chip of claim 19, wherein:

the test chip has p layers, each layer having n regions, at least some of the regions in each layer including respective nests of m parallel lines,

each of the p layers having m driver lines, the m driver lines connected to provide input signals to the respective m parallel lines in each nest in that respective layer,

each layer having at least 2n receiver lines, the at least 2n receiver lines connected to collectively receive output signals from all of the test structures in that respective layer.

22. The test chip of claim 21, wherein the receiver lines having corresponding connections in each respective one of the odd numbered layers are connected to each other.

23. The test chip of claim 22, wherein the test structures and receiver lines in the odd numbered layers are oriented in a common direction.

24. The test chip of claim 22, wherein the receiver lines having corresponding connections in each respective one of the even numbered layers are connected to each other.

25. The test chip of claim 24, wherein:

the test structures and receiver lines in the odd numbered layers are oriented in a first common direction; and

the test structures and receiver lines in the even numbered layers are oriented in a second common direction different from the first common direction.

26. The test chip of claim 19, wherein each test structure has four or fewer pins.

27. A test chip, comprising:

at least one layer having a vector of regions, each region capable of including at least one test structure, at least some of the regions including respective test structures,

the layer having a plurality of driver lines that provide input signals to the test structures,

the layer having a plurality of receiver lines that receive output signals from the test structures,

the layer having a plurality of devices for controlling current flow,

wherein each test structure is connected to at least one of the driver lines with a first one of the devices therebetween, and

each test structure is connected to at least one of the receiver lines with a second one of the devices therebetween, so that each of the test structures can be individually addressed for testing using the driver lines and receiver lines.

28. A test method, comprising the steps of:

(a) forming circuit paths for at least one level of a chip, the level having an m×

n array of regions, where m and n are integers, at least some of the regions including respective test structures,

(b) forming m+1 driver lines oriented in a first direction, each test structure being connected to at least one of the driver lines;

(c) forming 4n receiver lines arranged in a second direction, each test structure being connected to at least one of the receiver lines;

(d) individually addressing all the test structures using the m+1 driver lines and 4n receiver lines; and

(e) providing input signals to all of the test structures using the m+1 driver lines, and

(f) receiving output signals from all of the test structures using the 4n receiver lines.

29. The test method of claim 28, wherein:

each test structure has two inputs connected by respective diodes, transistors or controlled switches to a respective two of the driver lines, and

each test structure has two outputs connected by respective diodes, transistors or controlled switches to a respective two of the receiver lines.

30. The method of claim 28, wherein:

each test structure in the level is connected to at least one of the driver lines with a first diode therebetween,

each test structure in the level is connected to at least one of the receiver lines with a second diode therebetween,

step (e) includes performing as one of the group consisting of an inner loop and an outer loop a sequence of successively applying a first signal to each driver line of the level, one at a time, while applying a second signal to all remaining driver lines in the level; and

step (f) includes performing as the other of the group consisting of the inner loop and the outer loop a sequence of measuring a current to ground at each receiver line of the level, wherein the inner loop is performed each time the an iteration of the outer loop is performed.

31. The method of claim 28, wherein:

each test structure in the level is connected to at least one of the driver lines with a first transistor therebetween,

each test structure in the level is connected to at least one of the receiver lines with a second transistor therebetween, and

step (e) includes performing as one of the group consisting of an inner loop and an outer loop a sequence of successively applying a first voltage to each driver line of the level, one at a time, while applying a second voltage to all remaining driver lines in the level;

step (f) includes performing as the other of the group consisting of the inner loop and the outer loop a sequence of applying the second voltage to each receiver line of the level, one at a time, while applying the first voltage to all remaining receiver lines in the level; and

the method further comprises measuring a wafer substrate current to ground each time the second voltage is applied to a different receiver line in step (e).

32. The test method of claim 28, wherein:

the chip has p levels with test structures, where p is an integer greater than one, each of the p levels having m×

n regions, at least some of the regions in each level containing test structures,

the chip has p×

(m+1) driver lines, with each test structure connected to a respective at least one of the driver lines,

the chip has 8n receiver lines, with each test structure connected to a respective at least one of the receiver lines, and

step (d) includes individually addressing the p×

(m×

n) test structures for testing using the p×

(m+1) driver lines and 8n receiver lines.

33. The test method of claim 32, wherein:

the p levels include odd numbered levels and even numbered levels,

each level has 4n receiver lines,

and the method further comprises;

connecting the respective commonly positioned receiver lines from each of the odd numbered levels to each other, and

connecting the respective commonly positioned receiver lines from each of the even numbered levels to each other.

34. A test method, comprising the steps of:

(a) forming circuit paths for at least one layer having n regions, where n is an integer, each region capable of including at least one test structure, at least some of the regions including respective test structures, each comprising a nest of m parallel lines, where m is an integer,

(b) forming m driver lines for the at least one layer;

(c) forming at least 2n receiver lines for the at least one layer;

(d) providing input signals to the respective m parallel lines in each nest using the m driver lines;

(e) measuring output signals from all of the test structures using the at least 2n receiver lines; and

(f) identifying the presence of a short or open circuit defect in any of the nests based on the output signals received by way of the at least 2n receiver lines.

35. The test method of claim 34, wherein the layer has 3n receiver lines, and step (f) includes identifying the presence of a short or open circuit defect in any of the nests based on the output signals received by way of the 3n receiver lines.

36. The test method of claim 34, wherein:

the test chip has p layers, each layer having n regions, at least some of the regions in each layer including respective nests of m parallel lines,

each of the p layers having m driver lines, the m driver lines connected to provide input signals to the respective m parallel lines in each nest in that respective layer,

each layer having at least 2n receiver lines, the at least 2n receiver lines connected to collectively receive output signals from all of the test structures in that respective layer.

37. The test method of claim 36, further comprising connecting receiver lines having corresponding positions in each respective one of the odd numbered layers to each other.

38. The test method of claim 37, wherein the test structures and receiver lines in the odd numbered layers are oriented in a common direction.

39. The test method of claim 37, further comprising connecting receiver lines having corresponding positions in each respective one of the even numbered layers to each other.

40. The test method of claim 37, wherein:

the test structures and receiver lines in the odd numbered layers are oriented in a first common direction; and

the test structures and receiver lines in the even numbered layers are oriented in a second common direction different from the first common direction.

41. The test method of claim 34, wherein

each test structure in the layer is connected to at least one of the driver lines with a first transistor therebetween,

each test structure in the layer is connected to at least one of the receiver lines with a second transistor therebetween,

step (d) includes performing as one of the group consisting of an outer loop and an inner loop a sequence of successively applying a first voltage to each driver line of the layer, one at a time, while applying a second voltage to all remaining driver lines in the layer;

step (e) includes performing as the other of the group consisting of the outer loop and the inner loop a sequence of applying the second voltage to each receiver line of the layer, one at a time, while applying the first voltage to all remaining receiver lines in the layer; and

the method further comprises measuring a wafer substrate current to ground each time the second voltage is applied to a different receiver line in step (e).

42. The method of claim 34, wherein:

each test structure in the layer is connected to at least one of the driver lines with a first diode therebetween,

each test structure in the layer is connected to at least one of the receiver lines with a second diode therebetween,

and step (e) includes

performing as one of the group consisting of an inner loop and an outer loop a step of successively applying a first signal to each driver line of the level, one at a time, while applying a second signal to all remaining driver lines in the level; and

performing as the other of the group consisting of the inner loop and the outer loop a step of measuring a current to ground at each receiver line of the level.