Power semiconductor device having low gate input resistance

• US 8,178,923 B2
• Filed: 07/20/2010
• Issued: 05/15/2012
• Est. Priority Date: 05/27/2010
• Status: Active Grant

• Current Assignee: Sinopower Semiconductor, Inc.
• Original Assignee: Sinopower Semiconductor, Inc.
• Inventors: Lin, Wei-Chieh, Yang, Guo-Liang, Lin, Jia-Fu, Liao, Shian-Hau
• Primary Examiner(s): CHEN, JACK S J
• Application Number:
  US12/840,283
• Publication Number:
  US 20110291183A1
• Time in Patent Office: 665 Days
• Field of Search: 257/302, 257/328, 257/330, 257/341, 257773-776, 257/E29.262, 257/E21.41, 438/270
• US Class Current: 257/330
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/4925 with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with only a vertical doping structure or vertical doping variation H01L29/4916
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A power semiconductor device having low gate input resistance and a manufacturing method thereof are provided. The power semiconductor device includes a substrate, at least a trench transistor, a conductive layer, a metal contact plug, an insulating layer, an interlayer dielectric, a gate metal layer, and a source metal layer. The metal contact plug can serve as a buried gate metal bus line, and the metal contact plug can pass under the source metal layer and keeps the area of the source metal layer complete. Accordingly, the present invention can provide a lower gate input resistance without dividing the source metal layer, so the source metal layer can have a larger and complete area for the following packaging and bonding process.

Claims

1. A power semiconductor device having low gate input resistance, comprising:

a substrate, having an active region and a gate metal region, the substrate in the active region having at least a gate bus trench and a plurality of cell trenches, wherein the gate bus trench extends to the gate metal region, and the cell trenches and the gate bus trench are connected to each other;

at least a trench transistor, disposed in the active region of the substrate and at a side of the gate bus trench;

a conductive layer and a metal contact plug, disposed in the gate bus trench;

an insulating layer and an interlayer dielectric disposed on the substrate, wherein the insulating layer completely covers the metal contact plug in the active region, the insulating layer covers a portion of the gate metal region to expose a portion of the metal contact plug in the gate metal region, and the interlayer dielectric covers the conductive layer; and

a patterned metal layer disposed on the interlayer dielectric and the insulating layer, wherein the patterned metal layer comprises a gate metal layer and a source metal layer respectively disposed on the gate metal region and the active region, the gate metal layer is electrically connected to the metal contact plug for being configured to provide a gate voltage, and the source metal layer covers the insulating layer and is electrically connected to the trench transistor for being configured to provide a source voltage.

2. The power semiconductor device of claim 1, wherein the conductive layer is also disposed in the cell trenches.

3. The power semiconductor device of claim 2, further comprising a gate insulating layer disposed on a surface of the gate bus trench and the cell trenches, wherein the gate insulating layer is configured to isolate the conductive layer from the substrate.

4. The power semiconductor device of claim 1, further comprising at least a source contact plug disposed between two adjacent cell trenches, wherein the source contact plug is electrically connected to the source metal layer.

5. The power semiconductor device of claim 1, further comprising a drain metal layer disposed on a surface of the substrate opposite to the patterned metal layer.

6. The power semiconductor device of claim 1, wherein the conductive layer comprises doped polysilicon, and the metal contact plug comprises tungsten.