Semiconductor device
First Claim
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1. A semiconductor device, comprising:
- a semiconductor substrate having first and second main surfaces;
a first impurity region of a first conductivity type between said first main surface and said second main surface;
a second impurity region of a second conductivity type at said second main surface;
a first groove portion at said first main surface and reaching said first impurity region;
a first electrode in said first groove portion with a first insulating film interposed therebetween;
a second groove portion apart from said first groove portion and reaching said first impurity region from said first main surface;
a second electrode in said second groove portion with a second insulating film interposed therebetween;
a gate wiring connected to said first electrode and capable of applying a gate voltage to the first electrode;
a third impurity region of said first conductivity typed at a position of said first main surface adjacent to said first electrode on a side facing said second electrode;
a fourth impurity region of the second conductivity type at said first main surface between said first electrode and said second electrode and surrounding said third impurity region;
a main electrode on said first main surface and connected to said third impurity region and said fourth impurity region;
an interlayer insulating film on said first electrode and capable of insulating said main electrode and said first electrode from each other;
a fifth impurity region of the first conductivity type between said first and second electrodes and between said fourth impurity region and said first impurity region and having an impurity concentration higher than an impurity concentration of said first impurity region; and
a sixth impurity region of said second conductivity type at said first main surface adjacent to said second electrode on a side opposite to said fourth impurity region with respect to said second electrode, whereinsaid main electrode extends in the direction along which said first and second electrodes are aligned, and is connected to said second electrode, andsaid interlayer insulating film is on said sixth impurity region to insulate said sixth impurity region and said main electrode from each other.
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Abstract
There is provided a semiconductor device in which an amount of fluctuations in output capacitance and feedback capacitance is reduced. In a trench-type insulated gate semiconductor device, a width of a portion of an electric charge storage layer in a direction along which a gate electrode and a dummy gate are aligned is set to be at most 1.4 μm.
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Citations
29 Claims
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1. A semiconductor device, comprising:
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a semiconductor substrate having first and second main surfaces; a first impurity region of a first conductivity type between said first main surface and said second main surface; a second impurity region of a second conductivity type at said second main surface; a first groove portion at said first main surface and reaching said first impurity region; a first electrode in said first groove portion with a first insulating film interposed therebetween; a second groove portion apart from said first groove portion and reaching said first impurity region from said first main surface; a second electrode in said second groove portion with a second insulating film interposed therebetween; a gate wiring connected to said first electrode and capable of applying a gate voltage to the first electrode; a third impurity region of said first conductivity typed at a position of said first main surface adjacent to said first electrode on a side facing said second electrode; a fourth impurity region of the second conductivity type at said first main surface between said first electrode and said second electrode and surrounding said third impurity region; a main electrode on said first main surface and connected to said third impurity region and said fourth impurity region; an interlayer insulating film on said first electrode and capable of insulating said main electrode and said first electrode from each other; a fifth impurity region of the first conductivity type between said first and second electrodes and between said fourth impurity region and said first impurity region and having an impurity concentration higher than an impurity concentration of said first impurity region; and a sixth impurity region of said second conductivity type at said first main surface adjacent to said second electrode on a side opposite to said fourth impurity region with respect to said second electrode, wherein said main electrode extends in the direction along which said first and second electrodes are aligned, and is connected to said second electrode, and said interlayer insulating film is on said sixth impurity region to insulate said sixth impurity region and said main electrode from each other. - View Dependent Claims (2, 3, 4, 12, 13)
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5. A semiconductor device, comprising:
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a semiconductor substrate having first and second main surfaces; a first impurity region of a first conductivity type between said first main surface and said second main surface; a second impurity region of a second conductivity type at said second main surface; a first groove portion at said first main surface and reaching said first impurity region; a first electrode in said first groove portion with a first insulating film interposed therebetween; a second groove portion apart from said first groove portion and reaching said first impurity region from said first main surface; a second electrode in said second groove portion with a second insulating film interposed therebetween; a gate wiring connected to said first electrode and capable of applying a gate voltage to the first electrode; a third impurity region of said first conductivity typed at a position of said first main surface adjacent to said first electrode on a side facing said second electrode; a fourth impurity region of the second conductivity type at said first main surface located between said first electrode and said second electrode and surrounding said third impurity region; a main electrode on said first main surface and connected to said third impurity region and said fourth impurity region; an interlayer insulating film on said first electrode and capable of insulating said main electrode and said first electrode from each other; a fifth impurity region of the first conductivity type between said first and second electrodes and between said fourth impurity region and said first impurity region, and having an impurity concentration higher than an impurity concentration of said first impurity region and a width in a direction along which said first electrode and said second electrode are aligned of at most 1.4 μ
m;a third groove portion apart from said second groove portion; a third electrode in said third groove portion with a third insulating film interposed therebetween; a fourth groove portion provided apart from said third groove portion on a side opposite to said second groove portion with respect to said third groove portion; and a fourth electrode in said fourth groove portion with a fourth insulating film interposed therebetween, wherein said second electrode is connected to said gate wiring, and said fourth electrode is connected to said gate wiring, and said third electrode is connected to said main electrode. - View Dependent Claims (6, 7, 8, 9, 10, 11)
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14. A semiconductor device, comprising:
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a semiconductor substrate having first and second main surfaces; a first impurity region of a first conductivity type between said first main surface and said second main surface; a second impurity region of a second conductivity type at said second main surface; a first groove portion at said first main surface and reaching said first impurity region; a first electrode in said first groove portion with a first insulating film interposed therebetween; a second groove portion in said first main surface, apart from and on a first side of said first groove portion, and reaching said first impurity region; a second electrode in said second groove portion with a second insulating film interposed therebetween; a third groove portion in said first main surface, apart from and on a second side of said first groove portion opposite to said first side, and reaching said first impurity region; a third electrode in said third groove portion with a third insulating film interposed therebetween; a gate wiring connected to said first electrode and capable of applying a gate voltage to the first electrode; a third impurity region of said first conductivity type at said first main surface and positioned adjacent to said first electrode; a fourth impurity region of the second conductivity type at said first main surface between said first electrode and said second electrode and surrounding said third impurity region; a main electrode on said first main surface and electrically connected to said third impurity region and said second electrode; an interlayer insulating film on said first electrode and insulating said main electrode and said first electrode from each other; and a fifth impurity region of the first conductivity type having impurity concentration higher than impurity concentration of said first impurity region, positioned between said first and second electrodes and between said fourth impurity region and said first impurity region, and having a width in a direction along which said first electrode and said second electrode are aligned of at most 1.4 μ
m. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21, 22)
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23. A semiconductor device, comprising:
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a semiconductor substrate having first and second main surfaces; a first impurity region of a first conductivity type between said first main surface and said second main surface; a second impurity region of a second conductivity type at said second main surface; a first groove portion at said first main surface and reaching said first impurity region; a first electrode in said first groove portion with a first insulating film interposed therebetween; a second groove portion apart from said first groove portion and reaching said first impurity region from said first main surface; a second electrode in said second groove portion with a second insulating film interposed therebetween; a gate wiring connected to said first electrode and capable of applying a gate voltage to the first electrode; a third impurity region of said first conductivity type at a position of said first main surface adjacent to said first electrode on a side facing said second electrode; a fourth impurity region of the second conductivity type at said first main surface located between said first electrode and said second electrode and said third impurity region; a main electrode on said first main surface and connected to said third impurity region and said fourth impurity region; an interlayer insulating film on said first electrode and capable of insulating said main electrode and said first electrode from each other; a fifth impurity region of the first conductivity type between said first and second electrodes and between said fourth impurity region and said first impurity region, and having an impurity concentration higher than an impurity concentration of said first impurity region and a width in a direction along which said first electrode and said second electrode are aligned of at most 1.4 μ
m;a third groove portion apart from said second groove portion; a third electrode in said third groove portion with a third insulating film interposed therebetween; a fourth groove portion provided apart from said third groove portion on a side opposite to said second groove portion with respect to said third groove portion; and a fourth electrode in said fourth groove portion with a fourth insulating film interposed therebetween, wherein said second electrode is connected to said gate wiring, and said fourth electrode and said third electrode are connected to said main electrode. - View Dependent Claims (24, 25, 26, 27, 28, 29)
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Specification