Low fabrication cost, high performance, high reliability chip scale package

• US 8,178,967 B2
• Filed: 10/31/2007
• Issued: 05/15/2012
• Est. Priority Date: 09/17/2001
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lee, Jin-Yuan, Lei, Ming-Ta, Huang, Ching-Cheng, Lin, Chuen-Jye
• Primary Examiner(s): Cao, Phat X
• Application Number:
  US11/930,210
• Publication Number:
  US 20080099928A1
• Time in Patent Office: 1,658 Days
• Field of Search: 257/737, 257/738, 257/778, 257/780
• US Class Current: 257/737
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/02311 Additive methods
• CPC Class Codes: H01L 2224/03912 the bump being used as a mask for patterning the bonding area
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/11462 Electroplating
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/11831 involving a chemical process, e.g. etching the bump connector
• CPC Class Codes: H01L 2224/11849 Reflowing
• CPC Class Codes: H01L 2224/11901 with repetition of the same manufacturing step
• CPC Class Codes: H01L 2224/13017 being non uniform along the bump connector
• CPC Class Codes: H01L 2224/13023 the whole bump connector protruding from the surface
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73203 Bump and layer connectors
• CPC Class Codes: H01L 2224/85399 : Material
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/525 : with adaptable interconnections
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/12 : Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00013 : Fully indexed content
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01018 : Argon [Ar]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01041 : Niobium [Nb]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01084 : Polonium [Po]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/351 : Thermal stress
• CPC Class Codes: H04B 1/712 : Weighting of fingers for combining, e.g. amplitude control or phase rotation using an inner loop
• CPC Class Codes: H05K 2201/0367 : Metallic bump or raised conductor not used as solder bump solder materials or compositions and methods of application thereof H05K3/3457
• CPC Class Codes: H05K 2201/09436 : Pads or lands on permanent coating which covers the other conductors
• CPC Class Codes: H05K 2201/0949 : Pad close to a hole, not surrounding the hole if used for surface mounting H05K1/114
• CPC Class Codes: H05K 2203/043 : Reflowing of solder coated conductors, not during connection of components, e.g. reflowing solder paste
• CPC Class Codes: H05K 2203/054 : Continuous temporary metal layer over resist, e.g. for selective electroplating
• CPC Class Codes: H05K 3/108 : by semi-additive methods; masks therefor characterised by metallic etch mask H05K3/062; electroplating methods or apparatus H05K3/241
• CPC Class Codes: H05K 3/243 : characterised by selective plating, e.g. for finish plating of pads selective plating for making the circuit pattern H05K3/108, H05K3/182
• CPC Class Codes: H05K 3/3473 : Plating of solder

Abstract

The invention provides a new method and chip scale package is provided. The inventions starts with a substrate over which a contact point is provided, the contact point is exposed through an opening created in the layer of passivation and a layer of polymer or elastomer. A barrier/seed layer is deposited, a first photoresist mask is created exposing the barrier/seed layer where this layer overlies the contact pad and, contiguous therewith, over a surface area that is adjacent to the contact pad and emanating in one direction from the contact pad. The exposed surface of the barrier/seed layer is electroplated for the creation of interconnect traces. The first photoresist mask is removed from the surface of the barrier/seed layer. A second photoresist mask, defining the solder bump, is created exposing the surface area of the barrier/seed layer that is adjacent to the contact pad and emanating in one direction from the contact pad. The solder bump is created in accordance with the second photoresist mask, the second photoresist mask is removed from the surface of the barrier/seed layer, exposing the electroplating and the barrier/seed layer with the metal plating overlying the barrier/seed layer. The exposed barrier/seed layer is etched in accordance with the pattern formed by the electroplating, reflow of the solder bump is optionally performed.

Claims

1. A chip package comprising:

a ball grid array (BGA) substrate having a first side and a second side opposite to said first side;

a semiconductor device comprising a passivation layer, a polymer layer on said passivation layer and a metal pad having a contact point at a bottom of a first opening in said passivation layer, wherein said opening is over said contact point, wherein a second opening in said polymer layer is over said contact point;

a copper pillar between said semiconductor device and said first side, wherein said copper pillar is connected to said contact point through said first and second openings, wherein said copper pillar has a thickness between 10 and 100 micrometers;

a solder between said copper pillar and said first side, wherein said solder joins said first side;

a nickel layer between said copper pillar and said solder, wherein said nickel layer has a thickness between 1 and 10 micrometers, wherein said copper pillar has a sidewall recessed from that of said nickel layer, wherein said nickel layer comprises a first portion over said copper pillar and a second portion overhanging said copper pillar;

an underfill between said semiconductor device and said first side, wherein said underfill contacts said semiconductor device and said first side, said wherein said copper pillar has a sidewall with a region not covered by said solder bu covered by said underfill; and

a contact ball on said second side.

2. The chip package of claim 1, wherein said polymer layer comprises polyimide.

3. The chip package of claim 1, wherein said polymer layer comprises bisbenzocyclobutene (BCB).

4. The chip package of claim 1, wherein said metal pad comprises copper.

5. The chip package of claim 1, wherein said metal pad comprises aluminum.

6. A chip package comprising:

a substrate;

a semiconductor device comprising a separating layer, a polymer layer on said separating layer and a metal pad having a contact point at a bottom of a first opening in said separating layer, wherein said first opening is over said contact point, wherein a second opening in said polymer layer is over said contact point;

a copper pillar between said semiconductor device and said substrate, wherein said copper pillar is connected to said contact point through said first and second openings, and wherein said copper pillar has a thickness between 10 and 100 micrometers;

a solder between said copper pillar and said substrate, wherein said solder joins said substrate;

a nickel containing layer between said copper pillar and said solder;

a nickel-containing layer between said copper pillar and said solder, wherein said nickel-containing layer has a thickness between 1 and 10 micrometers, wherein said copper pillar has a sidewall recessed from that of said nickel-containing layer, wherein said nickel-containing layer comprises a first portion over said copper pillar and a second portion overhanging said copper pillar; and

an underfill between said semiconductor device and said substrate, wherein said underfill contacts said semiconductor device and said substrate, wherein said copper pillar has a sidewall with a region not covered by said solder but not covered by said underfill.

7. The chip package of claim 6, wherein said polymer layer comprises polyimide.

8. The chip package of claim 6, wherein said polymer layer comprises bisbenzocyclobutene (BCB).

9. The chip package of claim 6, wherein said metal pad comprises copper.

10. The chip package of claim 6, wherein said metal pad comprises aluminum.

11. A chip package comprising:

a ball grid array (BGA) substrate having a first side and a second side opposite to said first side;

a semiconductor device comprising a passivation layer, a polymer layer on said passivation layer, a metal pad having a contact point at a bottom of a first opening in said passivation layer, wherein said first opening is over said contact point, wherein a second opening in said polymer layer is over said contact point, and a metal interconnect on said polymer layer and said contact point, wherein said metal interconnect is connected to said contact point through second opening;

a copper pillar between said semiconductor device and said first side, and vertically over said metal interconnect, wherein said copper pillar is connected to said contact point through said metal interconnect, and wherein said metal interconnect has a top surface with a first region vertically under said copper piller, and a second region not vertically under said copper pillar, wherein said copper pillar has a thickness between 10 and 100 micrometers;

a solder between said copper pillar and said first side, wherein said solder joins said first side;

a nickel layer between said copper pillar and said first side, wherein said nickel layer has a thickness between 1 and 10 micrometers, wherein said copper pillar has a sidewall recessed from that of said nickel layer, wherein said nickel layer comprises a first portion over said copper pillar and a second portion overhanging said copper pillar;

an underfill between said semiconductor device and said first side, wherein said underfill contacts said semiconductor device and said first side, wherein said copper pillar has a sidewall with a region not covered by said solder but covered by said underfill; and

a contact ball on said second side.

12. The chip package of claim 11, wherein said polymer layer comprises polyimide.

13. The chip package of claim 11, wherein said metal interconnect comprises titanium.

14. The chip package of claim 11, wherein said metal pad comprises copper.

15. The chip package of claim 11, wherein said metal interconnect comprises a first metal layer comprising a titanium-containing material and a second metal layer on said first metal layer.

16. A chip package comprising:

a substrate;

a semiconductor device comprising a passivation layer, a polymer layer on said passivation layer, a metal pad having a contact point at a bottom of a first opening in said passivation layer, wherein said first opening is over said contact point, wherein a second opening in said polymer layer is over said contact point, and a metal interconnect on said polymer layer and said contact point, wherein said metal interconnect is connected to said contact point through said second opening;

a copper pillar between said semiconductor device and said substrate and vertically over said metal interconnect, wherein said copper pillar is connected to said contact point through said metal interconnect, wherein said metal interconnect has a top surface with a first region vertically under said copper pillar and a second region not vertically under said copper pillar, wherein said copper pillar has a thickness between 10 and 100 micrometers;

a solder between said copper pillar and said substrate, wherein said solder joins said substrate;

a nickel-containing layer between said copper pillar and said solder, wherein said nickel-containing layer has a thickness between 1 and 10 micrometers, wherein said copper pillar has a sidewall recessed from that of said nickel-containing layer, wherein said nickel-containing layer comprises a first portion over said copper pillar and a second portion overhanging said copper pillar; and

an underfill between said semiconductor device and said substrate, wherein said underfill contacts said semiconductor device and-said substrate, wherein said copper pillar has a sidewall with a region not covered by said solder but covered by said underfill.

17. The chip package of claim 16, wherein said polymer layer comprises polyimide.

18. The chip package of claim 16, wherein said metal interconnect comprises titanium.

19. The chip package of claim 16, wherein said metal pad comprises copper.

20. The chip package of claim 16, wherein said metal interconnect comprises a first metal layer comprising a titanium-containing material and a second metal layer on said first metal layer.

21. A chip package comprising:

a substrate;

a semiconductor device comprising a passivation layer, a metal pad having a contact point at a bottom of an opening in said passivation layer, wherein said metal pad comprises copper, wherein said opening is over said contact point, and a metal interconnect over said passivation layer and on said contact point, wherein said metal interconnect is connected to said contact point through said opening;

a copper pillar between said semiconductor device and said substrate and vertically over said metal interconnect, wherein said copper pillar is connected to said contact point through said metal interconnect, wherein said metal interconnect has a top surface with a first region vertically under said copper pillar and a second region not vertically under said copper pillar, wherein said copper pillar has a thickness between 10 and 100 micrometers;

a solder between said copper pillar and said substrate, wherein said solder joins said substrate;

a nickel-containing layer between said copper pillar and said solder, wherein said nickel- containing layer has a thickness between 1 and 10 micrometers, wherein said copper pillar has a sidewall recessed from that of said nickel-containing layer, wherein said nickel-containing layer comprises a first portion over said copper pillar and a second portion overhanging said copper pillar; and

an underfill between said semiconductor device and said substrate, wherein said underfill contacts said semiconductor device and said substrate, wherein said copper pillar has a sidewall with a region not covered by said solder but covered by said underfill.

22. The chip package of claim 21 further comprising a nickel-containing layer between said copper pillar and said solder.

23. The chip package of claim 21, wherein said substrate comprises a ball grid array (BGA) substrate.