Current-feedback instrumentation amplifiers

• US 8,179,195 B1
• Filed: 01/24/2011
• Issued: 05/15/2012
• Est. Priority Date: 01/24/2011
• Status: Active Grant

• Current Assignee: Maxim Integrated Products, Inc. (Analog Devices, Inc.)
• Original Assignee: Maxim Integrated Products, Inc. (Analog Devices, Inc.)
• Inventors: Huijsing, Johan Hendrik, Wu, Rong, Makinwa, Kofi A. A.
• Primary Examiner(s): NGUYEN, PATRICIA T
• Application Number:
  US13/012,550
• Time in Patent Office: 477 Days
• Field of Search: 330/9, 330/124.R, 330/295, 330/126
• US Class Current: 330/9
• CPC Class Codes: H03F 2200/261 Amplifier which being suitable for instrumentation applications
• CPC Class Codes: H03F 2200/411 the output amplifying stage of an amplifier comprising two power stages
• CPC Class Codes: H03F 2200/513 the amplifier being made for low supply voltages
• CPC Class Codes: H03F 2203/45366 the AAC comprising multiple transistors parallel coupled at their gates only, e.g. in a cascode dif amp, only those forming the composite common source transistor
• CPC Class Codes: H03F 2203/45422 the CMCL comprising one or more capacitors not as integrating capacitor, e.g. for stability purposes
• CPC Class Codes: H03F 2203/45512 the FBC comprising one or more capacitors, not being switched capacitors, and being coupled between the LC and the IC
• CPC Class Codes: H03F 2203/45536 the FBC comprising a switch and being coupled between the LC and the IC
• CPC Class Codes: H03F 3/38 DC amplifiers with modulator at input and demodulator at output; Modulators or demodulators specially adapted for use in such amplifiers switched capacitor amplifiers H03F3/005
• CPC Class Codes: H03F 3/423 with MOSFET's
• CPC Class Codes: H03F 3/45237 Complementary long tailed pairs having parallel inputs and being supplied in series
• CPC Class Codes: H03F 3/45475 using IC blocks as the active amplifying circuit
• CPC Class Codes: H03F 3/45941 Controlling the input circuit of the differential amplifier

Abstract

Current-feedback instrumentation amplifiers that include dynamic element matching for the input transconductance amplifiers by periodically swapping the transconductance amplifiers between the instrumentation amplifier input and the feedback input. The instrumentation amplifiers may include a gain error reduction loop, which loop corrects differences in the gains of the input transconductance amplifiers and eliminates the ripple in the instrumentation amplifier output caused by the dynamic element matching. If chopper stabilization is used, the amplifiers may also include an offset reduction loop. Various embodiments are disclosed.

Claims

1. A current feedback instrumentation amplifier (CFIA) having a differential signal input, a differential feedback input and an output comprising:

first and second transconductance amplifiers, each having a differential input and a differential output;

the first and second transconductance amplifiers having their differential outputs coupled together and to the output of the CFIA;

first circuitry coupled to the differential signal input and the differential feedback input to periodically swap the differential inputs of the first and second transconductance amplifiers between the differential signal input and the differential feedback input, respectively, at a first frequency.

2. The CFIA of claim 1 further comprising:

a comparator having an input coupled to the output of the CFIA;

second circuitry coupled to an output of the comparator and to the output of the CFIA, the second circuitry chopping an output signal of the CFIA at the first frequency and coupling the chopped signal to a gain control input of the first and/or second transconductance amplifiers with a polarity responsive to an output of the comparator.

3. The CFIA of claim 2 wherein the second circuitry is capacitively coupled to the output of the CFIA.

4. The CFIA of claim 3 wherein the output of the second circuitry is coupled to a gain control input of the first and/or second transconductance amplifiers through a first integrator.

5. The CFIA of claim 4 wherein the first integrator is an analog integrator.

6. The CFIA of claim 4 wherein the first integrator is a digital integrator preceded by an analog to digital converter and followed by a digital to analog converter.

7. The CFIA of claim 6 wherein the operation of the first integrator is frozen in a region around a zero output of the CFIA.

8. The CFIA of claim 1 further comprising:

a comparator having an input coupled to the output of the CFIA and an output having a comparison output and a digital integrator enable output;

an analog to digital converter;

second circuitry coupled to the comparison output of the comparator, to the output of the CFIA and to the analog to digital converter input, the second circuitry to demodulate a signal at the output of the CFIA at a first frequency and to couple the demodulated signal to an input of an analog to digital converter with a polarity responsive to the comparison output of the comparator;

an analog to digital converter output being coupled to an input of a digital integrator;

the digital integrator, when enabled, integrating the output of the analog to digital converter;

a digital to analog converter having an input coupled to an output of the digital integrator and an output coupled to a gain control input of the first and/or second transconductance amplifiers.

9. The CFIA of claim 8 wherein the second circuitry is capacitively coupled to the output of the CFIA.

10. The CFIA of claim 1 further comprising:

a comparator having an input coupled to the output of the CFIA and an output having a comparison output and a counter enable output;

a counter having an enable input coupled to the counter enable output of the comparator and an up/down counter input;

second circuitry coupled to the comparison output of the comparator, to the output of the CFIA and to the up/down counter input, the second circuitry to demodulate a signal at the output of the CFIA at a first frequency and to couple the demodulated signal to the up/down counter input with a polarity responsive to the comparison output of the comparator;

the counter, when enabled, counting up or down responsive the up/down counter input;

a digital to analog converter having an input coupled to the output of the counter and an output coupled to a gain control input of the first and/or second transconductance amplifiers.

11. The CFIA of claim 1 further comprising:

a first chopper;

the first circuitry being coupled to the differential signal input and the differential feedback input to chop the differential signal input and the differential feedback input at a second frequency, and to swap the differential inputs of the first and second transconductance amplifiers between the chopped differential signal input and the chopped differential feedback input, respectively, at the first frequency;

the first chopper being coupled between the outputs of the first and second transconductance amplifiers and the output of the CFIA to chop the outputs of the first and second transconductance amplifiers at the second frequency;

the second frequency being N times the first frequency, where N is an integer.

12. The CFIA of claim 11 further comprising:

a comparator having an input coupled to the output of the CFIA;

second circuitry coupled to an output of the comparator and to the output of the CFIA, the second circuitry chopping an output signal of the CFIA at the first frequency and coupling the chopped output signal of the CFIA to a gain control input of the first and/or second transconductance amplifiers with a polarity responsive to an output of the comparator.

13. The CFIA of claim 12 wherein the output of the second circuitry is coupled to a gain control input of the first and/or second transconductance amplifiers through a first integrator.

14. The CFIA of claim 13 wherein the first integrator is an analog integrator.

15. The CFIA of claim 13 wherein the first integrator is a digital integrator preceded by an analog to digital and followed by a digital to analog.

16. The CFIA of claim 15 wherein the operation of the first integrator is frozen in a region around a zero output of the CFIA.

17. The CFIA of claim 12 further comprising:

an oscillator coupled to the first and second circuitry and to the first chopper for causing the first circuitry to chop the differential signal input and the differential feedback input a full number N of chopper clock cycles at a second frequency, then swap the differential inputs of the first and second transconductance amplifiers between the chopped differential signal input and the chopped differential feedback input, respectively, and again chop the differential signal input and the differential feedback input the same full number N of chopper clock cycles at the second frequency, to provide the second frequency to the first chopper, and to provide the first frequency to the second circuitry.

18. The CFIA of claim 12 wherein the first circuit comprises second through fifth choppers, the second and third choppers having their differential inputs coupled to the differential signal input and the fourth and fifth choppers having their differential inputs coupled to the differential feedback signal, the second and fourth choppers having their differential outputs coupled to the differential input of the first transconductance amplifier and the third and fifth choppers having their differential outputs coupled to the differential inputs of the second transconductance amplifier, the second and fifth choppers being operated simultaneously at the second frequency while the third and fourth choppers are inactive, and the third and fourth choppers being operated simultaneously at the second frequency while the second and fifth choppers are inactive.

19. The CFIA of claim 12 wherein the second circuitry is capacitively coupled to the output of the CFIA.

20. The CFIA of claim 12 wherein the output of the first chopper is coupled to the output of the CFIA through at least one additional transconductance amplifier.

21. The CFIA of claim 12 further comprising:

a second chopper having a differential input coupled to the output of the CFIA and a differential output coupled to a differential integrator, the second chopper chopping a signal on the output of the CFIA at the second frequency;

each of the differential outputs of the differential integrator being coupled to a respective one of the differential outputs of the first and second transconductance amplifiers.

22. The CFIA of claim 21 wherein the differential input of the second chopper is capacitively coupled to the output of the CFIA.

23. The CFIA of claim 21 wherein the differential output of the integrator is coupled to the differential outputs of the first and second transconductance amplifiers through another transconductance amplifier.

24. The CFIA of claim 11 further comprising:

a comparator having a differential input coupled to the output of the CFIA and an output having a comparison output and a counter enable output;

a counter having an enable input coupled to the counter enable output of the comparator and an up/down counter input;

second circuitry coupled to the comparison output of the comparator, to the output of the CFIA and to the up/down counter input, the second circuitry to demodulate a signal at the output of the CFIA at the first frequency and to couple the demodulated signal to the up/down counter input with a polarity responsive to the comparison output of the comparator;

the counter, when enabled, counting up or down responsive the up/down counter input;

a digital to analog converter having an input coupled to the output of the counter and an output being coupled to a gain control input of the first and/or second transconductance amplifiers.

25. The CFIA of claim 24 further comprising:

a second chopper having a differential input coupled to the output of the CFIA and a differential output coupled to an integrator, the second chopper chopping a signal at the output of the CFIA at the second frequency;

each of the differential outputs of the differential integrator being coupled to a respective one of the differential outputs of the first and second transconductance amplifiers.

26. The CFIA of claim 25 wherein the differential input of the second chopper is capacitively coupled to the output of the CFIA.

27. The CFIA of claim 25 wherein the differential output of the integrator is coupled to the differential outputs of the first and second transconductance amplifiers through another transconductance amplifier.