Digital readout method and apparatus

• US 8,179,296 B2
• Filed: 05/01/2006
• Issued: 05/15/2012
• Est. Priority Date: 09/30/2005
• Status: Active Grant

• Current Assignee: Massachusetts Institute of Technology
• Original Assignee: Massachusetts Institute of Technology
• Inventors: Kelly, Michael, Mooney, Daniel, Colonero, Curtis, Berger, Robert, Candell, Lawrence
• Primary Examiner(s): Jean Pierre, Peguy
• Application Number:
  US11/415,007
• Publication Number:
  US 20070075888A1
• Time in Patent Office: 2,206 Days
• Field of Search: 341/155, 341/157, 341/161, 341/163, 250/214, 250/208.1
• US Class Current: 341/155
• CPC Class Codes: H03M 1/12 Analogue/digital converters H03M1/001 – H03M1/10 take precedence
• CPC Class Codes: H03M 1/145 the steps being performed sequentially in series-connected stages H03M1/141, H03M1/143, H03M1/16 take precedence
• CPC Class Codes: H03M 1/60 with intermediate conversion to frequency of pulses
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 25/772 comprising A/D, V/T, V/F, I/T or I/F converters

Abstract

Autonomously operating analog to digital converters are formed into a two dimensional array. The array may incorporate digital signal processing functionality. Such an array is particularly well-suited for operation as a readout integrated circuit and, in combination with a sensor array, forms a digital focal plane array.

Claims

1. An apparatus comprising:

a sensor array comprised of a plurality of sensing elements; and

a plurality of analog-to-digital converters (ADCs) arranged in a two-dimensional ADC array, each ADC within the ADC array being operably coupled to a respective sensing element and comprising;

(i) a capacitance to integrate current generated by the respective sensing element and

(ii) a converter operably coupled to the capacitance and configured to convert an analog signal from the capacitance to a series of pulse.

2. The apparatus of claim 1 further comprising digital signal processing circuitry configured to operate on the digital output of the ADCs.

3. The apparatus of claim 1 wherein the ADC array is implemented by a silicon CMOS process.

4. The apparatus of claim 1 further comprising;

an analyzer configured to receive and analyze data from the ADC array.

5. The apparatus of claim 1 further comprising;

a storage system configured to store information produced by the ADC array.

6. The apparatus of claim 1 wherein each ADC further includes a counter operably coupled to the converter and configured to increment or decrement a digital count response to the series of pulses.

7. The aparatus of claim 6 wherein the counter is a ripple counter.

8. The apparatus of claim 6 wherein each ADC further includes a shift register operably coupled to the counter and configured to operate on a digital output from the counter.

9. The apparatus of claim 1, wherein

each ADC within the ADC array is further configured to transfer digital data to at least one neighboring ADC within the ADC array.

10. The apparatus of claim 9 wherein the,apparatus is further configured to perform a mathematical operation by transferring digital data among ADCs in the ADC array and by incrementing or decrementing at least one count stored in an ADC in the ADC array.

11. The apparatus of claim 10 wherein the mathematical operation is a convolution.

12. The apparatus of claim 9 wherein each ADC within the two-dimensional ADC array is further configured to transfer digital data to each of its neighbor ADCs within the two-dimensional ADC array.

13. The apparatus of claim 1 wherein the apparatus is configured to operate as a member of a group consisting of a camera, a surveillance system, a recognition system, a robotic manufacturing system, a chemical detection system, a biological detection system, and an optical computer.

14. The apparatus of claim 1 wherein the capacitance of each ADC. within the ADC array defines the least significant bit of the ADC.

15. The apparatus of claim 1 wherein the capacitance has a value of about 1 femtofarad to about 10 femtofarads.

16. The apparatus of claim 1 wherein the capacitance is defined by a parasitic capacitance.

17. A method of analog-to-digital conversion, the method comprising:

generating an analog signal at a sensing element in a plurality of sensing elements;

transferring the analog signal from the sensing element to a corresponding, analog-to-digital converter (ADC) in a plurality of analog-to-digital converters (ADCS) arranged in a two-dimensional array;

integrating the analog signal in a capacitance in the corresponding ADC;

converting charge integrated in the capacitance into digital data representative of the analog signal;

measuring motion of the plurality of sensing elements; and

compensating for the measured motion by transferring digital data among adjacent ADCs in the two-dimensional array.

18. A method of analog-to-digital conversion, the method comprising:

generating an analog signal at a sensing element in a plurality of sensing elements;

transferring the analog signal from the sensing element to a corresponding analog-to-digital converter (ADC) in a plurality of analog-to-digital converters (ADCs) arranged in a two-dirriensional array;

integrating the analog signal in a capacitance in the corresponding ADC;

discharging the capacitance to produce a current; and

converting the current into a series of pulses.

19. The method of claim 18 further including incrementing or decrementing a count based on the series of pulses to provide digital data representative of the analog signal.

20. The method of claim 19 further comprising;

transferring at least a subset of the data between adjacent ADCs in the two-dimensional array.

21. The method of claim 19 further comprising:

performing a mathematical operation on at least a subset of the digital data by transferring the subset of the digital data between ADCs and by incrementing or decrementing a count in at least one ADC.

22. The method of claim 21 wherein performing the mathematical operation includes performing a convolution.

23. The method of claim 18 wherein the capacitance of each ADC within the ADC array defines the least significant bit of the ADC.

24. The method of claim 18 wherein the capacitance has a value of about 1 femtofarad to about 10 femtofarads.

25. The method of claim 18 wherein the capacitance is defined by a parasitic capacitance.

26. The method claim 18 further comprising discharging the capacitance to a predetermined threshold level.

27. An apparatus for processing data, the apparatus comprising:

a plurality of analog-to-digital converters (ADCs) arranged in a two-dimensional array, each ADC in the plurality of ADCs being associated with a respective counter and configured to decrement a count in its respective counter,

wherein each ADC in the plurality of ADCs is configured to transfer data from its respective counter to one or more adjacent ADCs in the two-dimensional array.

28. The apparatus of claim 27 wherein each ADC is further configured to increment the count stored in its respective counter.

29. The apparatus of claim 27 wherein each counter is configured to store n bits, and wherein the plurality of ADCs is configured to perform modulo n arithmetic.

30. The apparatus of claim 27 further comprising a sensor array operably coupled to the plurality or ADCs.

31. The apparatus of claim 30,

wherein the plurality of ADCs is configured to filter data from the sensor array.

32. An apparatus for processing data, the apparatus comprising:

a plurality of analog-to-digital converters (ADCs) arranged in a two-dimensional array each ADC in the plurality of ADCs being associated with a respective counter and configured to decrement a count in its respective counter,

wherein each ADC in the plurality of ADCS is configured to control an accumulation time of its respective counter.

33. A method for processing data in a plurality of analog-to-digital converters (ADCs) arranged in a two-dimensional array, each ADC in the two-dimensional array including a counter, the method comprising:

generating digital data that represents an analog signal using, at least one of the ADCs in the two-dimensional array of ADCs;

decrementing a count in at least one of the counters based on the digital data;

storing n bits in at least one of the counters; and

performing modulo n arithmetic on the stored bits using the plurality of ADCs.

34. The method of claim 33 further comprising:

incrementing the count based on the digital data.

35. The method of claim 33 further comprising:

controlling an accumulation time of at least one of the counters.

36. The method of claim 33 further comprising.

transferring digital data between adjacent ADCs in the two-dimensional array.

37. The method of claim 33 further comprising:

transferring the analog signal from a sensor array to the plurality of ADCs.

38. The method of claim 37 further comprising:

filtering the analog signal using at least one of the plurality of ADCs.

39. An apparatus comprising:

a sensor array comprising a plurality of sensing elements; and

a plurality of analog-to-digital converters (ADCs) arranged in a two-dimensional ADC array, each ADC within the ADC array being operably coupled to a respective sensing element to receive an analog input, each ADC being further configured to generate a digital output based on the analog input, without an analog ramp signal or analog reference signal supplied by an outside source external to the ADC.

40. The apparatus of claim 39 wherein each ADC within the ADC array comprises a capacitor to integrate the analog input from the respective sensing element to a level that produces at least one output pulse.

41. The apparatus of claim 40 wherein each ADC within the ADC array further comprises a counter operably coupled to the capacitor and configured to count the at least one output pulse from the capacitor.

42. A method of analog-to-digital conversion, the method comprising:

generating an analog signal at a sensing element in a plurality of sensing elements;

transferring the analog signal from the sensing element to a corresponding analog-to-digital converter (ADC) in a plurality of analog-to-digital, converters (ADCs) arranged, in a two-dimensional array; and

generating at the corresponding ADC digital data representative of the analog signal without comparing the analog signal to anonalog ramp signal or analog reference signal supplied by an outside source external to the corresponding ADC.

43. The method of claim 42, further comprising:

integrating the analog signal in a capacitor in the corresponding ADC to a level that produces at least one output pulse.

44. The method of claim 43, further comprising:

counting the at least one output pulse from the capacitor with a counter in the corresponding ADC.