Liquid crystal display device and fabricating method thereof

• US 8,179,510 B2
• Filed: 06/29/2005
• Issued: 05/15/2012
• Est. Priority Date: 12/31/2004
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Display Co., Ltd.
• Inventors: Ahn, Byung Chul, Lim, Byoung Ho, Ahn, Jae Jun
• Primary Examiner(s): Nguyen, Lauren
• Application Number:
  US11/168,358
• Publication Number:
  US 20060146212A1
• Time in Patent Office: 2,512 Days
• Field of Search: 349/141, 349/149, 349/152, 349/187
• US Class Current: 349/141
• CPC Class Codes: G02F 1/134363 for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
• CPC Class Codes: G02F 1/136231 for reducing the number of lithographic steps
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence

Abstract

A liquid crystal display device having first and second substrates; a gate line on the first substrate; a data line crossing the gate line to define a pixel area, the gate line and the data line having a gate insulating film there between; a thin film transistor including a gate electrode, a source electrode, a drain electrode and a semiconductor layer for defining a channel between the source electrode and the drain electrode; a common line in parallel to the gate line on the first substrate; a common electrode extended from the common line in the pixel area; and a pixel electrode spaced apart from the common line and the common electrode in the pixel area to be defined in a pixel hole passing through the gate insulating film, wherein the semiconductor layer overlaps with a source and drain metal pattern including the data line, the source electrode and the drain electrode, and wherein the drain electrode protrudes from the semiconductor layer toward an upper portion of the pixel electrode to be connected to the pixel electrode.

Claims

1. A method of fabricating a liquid crystal display device, comprising:

providing first and second substrates;

a first mask process of forming a first mask pattern group including a gate line, a gate electrode, a common line, a common electrode, a data link and a lower pad electrode to be connected to the data line on the first substrate;

a second mask process of forming a gate insulating film and a semiconductor layer on the first mask pattern group formed by the first mask process, defining a pixel hole spaced apart from the common line and a common electrode to pass through the gate insulating film and the semiconductor layer in a pixel area thereby exposing a surface of the first substrate, forming first and second contact holes for exposing the lower pad electrode and the data link and forming an upper pad electrode connected to the lower pad electrode and a contact electrode to be connected to the data link and the data line in the corresponding contact hole, and forming a pixel electrode to be contacted with the surface of the first substrate and a side wall of the gate insulating film exposed through the pixel hole in the pixel hole; and

a third mask process of forming a source and drain metal pattern including a data line crossing the gate line to define the pixel area, a source electrode and a drain electrode on the first substrate, and exposing an active layer of the semiconductor pattern to define a channel between the source electrode and the drain electrode,

wherein a portion of the drain electrode covers a part of upper surface of the pixel electrode at bottom part of the pixel hole,

wherein the first to third mask processes are sequentially performed, and wherein the second mask process includes;

forming a photo-resist pattern on the semiconductor layer;

forming the pixel hole and the first and second contact holes using the photo-resist pattern as a mask;

forming a transparent conductive film on the photo-resist pattern, and forming transparent conductive patterns in the pixel hole and the first and second contact holes; and

removing the photo-resist pattern with the transparent conductive film formed on the photo-resist pattern.

2. The method as claimed in claim 1, wherein the gate line, the gate electrode and the common line have at least double conductive layers including a transparent conductive layer, and the common electrode is formed by an extension of the transparent conductive layer of the common line.

3. The method as claimed in claim 1, wherein the gate line and the common line are formed of a metal layer.

4. The method as claimed in claim 1, wherein the pixel electrode borders with the gate insulating film in the pixel hole.

5. The method as claimed in claim 1, wherein the first mask process comprises:

forming the at least double conductive layer on the first substrate;

forming photo-resist patterns having a different thickness by a photolithography using a partial transmitting mask;

forming the first mask pattern group including the common electrode having the at least double conductive layer by an etching process using the photo-resist pattern; and

etching the common electrode to leave a transparent conductive layer thereof by said etching process using the photo-resist pattern.

6. The method as claimed in claim 1, wherein the third mask process further includes:

allowing the semiconductor layer to exist in the channel and an overlapping portion between the source and drain metal pattern and the gate insulating film.

7. The method as claimed in claim 6, wherein the third mask process includes:

forming a source and drain metal pattern including a data line and a drain electrode being integral to the source electrode on the first substrate;

etching a semiconductor layer exposed through the source and drain metal pattern; and

exposing the active layer between the source and drain electrodes to define the channel.

8. The method as claimed in claim 6, wherein the third mask process includes:

forming a source and drain metal layer on the first substrate and forming photo-resist pattern having a different thickness thereon;

patterning the source and drain metal layer through the photo-resist patterns to provide the source and drain metal pattern including the data line and the drain electrode being integral to the source electrode;

etching a semiconductor layer exposed through the photo-resist patterns; and

exposing the active layer between the source and drain electrodes through the photo-resist patterns to form the channel.

9. The method as claimed in claim 1, wherein the third mask process further includes:

forming a storage capacitor such that the drain electrode overlaps with a portion of the common electrode, the gate insulating film and the semiconductor layer.

10. The method as claimed in claim 1, wherein:

the first mask process further includes forming a lower pad electrode connected to at least one of the gate line and the common line, and

the second mask process further includes forming a contact hole for exposing the lower pad electrode and forming an upper pad electrode connected to the lower pad electrode in the contact hole.

11. The method as claimed in claim 1, wherein the first contact hole with the upper pad electrode is extended along the data link to be integral to the second contact hole, and the upper pad electrode is integral to the contact electrode.

12. The method as claimed in claim 1, wherein a transparent conductive pattern including at least one of the pixel electrode, the upper pad electrode and the contact electrode border with the gate insulating film enclosing the corresponding contact hole.

13. The method as claimed in claim 10, wherein a transparent conductive pattern including at least one of the pixel electrode, the upper pad electrode and the contact electrode border with the gate insulating film enclosing the contact hole.

14. The method as claimed in claim 1, wherein a contact portion between the data line and the contact electrode is in an area to be sealed by a sealant upon joining of the first substrate with the second substrate.

15. The method as claimed in claim 11, wherein a contact portion between the data line and the contact electrode is in an area to be sealed by a sealant upon joining of the first substrate with the second substrate.

16. The method as claimed in claim 1, wherein the second mask process further includes:

forming a contact hole passing through the semiconductor layer and the gate insulating film and to be overlapped with the data line; and

forming a pad to be connected to the data line in the contact hole.

17. The method as claimed in claim 16, wherein the pad borders with the gate insulating film enclosing the contact hole.

18. The method as claimed in claim 16, wherein the data line is in an area to be sealed by a sealant upon joining of the first substrate with the second substrate.

19. The method as claimed in claim 1, wherein the third mask process further includes:

surface treating the channel of the thin film transistor with plasma to oxidize the surface layer.

20. The method as claimed in claim 6, wherein the semiconductor layer and the source and drain metal pattern have a shape.

21. The method as claimed in claim 10, wherein the second mask process includes:

forming a photo-resist pattern on the semiconductor layer;

forming the pixel hole and the contact hole using the photo-resist pattern as a mask;

forming a transparent conductive film on the photo-resist pattern, and forming the corresponding transparent conductive pattern in the pixel hole and the contact hole; and

removing the photo-resist pattern formed with the transparent conductive film.

22. The method as claimed in claim 21, wherein the semiconductor layer and the gate insulating film are over-etched such that the edges of the pixel hole and the contact hole are positioned at the inner side than the photo-resist pattern.

23. The method as claimed in claim 21, further comprising:

a fourth mask process of forming a protective film on the first substrate and opened at a pad area where a pad is to be formed.

24. The method as claimed in claim 21, further comprising:

printing the protective film on the first substrate in such a manner as to be opened at a pad area where a pad is to be formed.

25. The method as claimed in claim 21, further comprising:

forming the protective film on the first substrate;

forming an alignment film on the protective film; and

removing the protective film at a pad area by an etching using the alignment film as a mask.

26. The method as claimed in claim 21, further comprising:

forming the protective film on the first substrate;

attaching the first and second substrates; and

removing the protective film at a pad area by an etching using the second substrate as a mask.

27. The method as claimed in claim 1, wherein the semiconductor layer and the gate insulating film are over-etched such that the edges of the pixel hole and the contact hole are positioned at the inner side than the photo-resist pattern.

28. The method as claimed in claim 1, further comprising:

a fourth mask process of forming a protective film on the first substrate and opened at a pad area provided with the pad.

29. The method as claimed in claim 1, further comprising:

printing the protective film on the first substrate in such a manner as to be opened at a pad area provided with the pad.

30. The method as claimed in claim 1, further comprising:

forming the protective film on the first substrate;

forming an alignment film on the protective film; and

removing the protective film at a pad area by an etching using the alignment film as a mask.

31. The method as claimed in claim 1, further comprising:

forming the protective film on the first substrate;

attaching the first and second substrates; and

removing the protective film at a pad area by an etching using the second substrate as a mask.

32. The method as claimed in claim 1, further comprising:

forming a liquid crystal layer between the first and second substrates.