Method for clock and data recovery

• US 8,180,007 B2
• Filed: 01/14/2010
• Issued: 05/15/2012
• Est. Priority Date: 01/14/2010
• Status: Expired due to Fees

• Current Assignee: North Star Innovations Inc. (Wi-LAN Inc.)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Iqbal, Asif, Agrawal, Girraj K., Pal, Ankit
• Primary Examiner(s): Flores, Leon
• Application Number:
  US12/687,844
• Publication Number:
  US 20110170644A1
• Time in Patent Office: 852 Days
• Field of Search: 375/316, 375/340, 375/354, 375/355, 375/360, 370/503, 370/508, 370/509, 370/510, 370/511, 370/512, 370/513, 370/514, 455/502, 327/141, 713/375
• US Class Current: 375/355
• CPC Class Codes: H04L 7/0337 Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Abstract

An input bit stream including a clock signal and data bits is oversampled to obtain one or more sets of data samples. One or more sets of non-transitioning phases corresponding to data samples that do not switch between zero and one are then identified. Center phases corresponding to the one or more sets of non-transitioning phases are identified and then a final center phase that accurately represents the bits belonging to the input bit stream is selected. The data samples corresponding to the final center phase are extracted, thereby recovering the clock signal and data bits from the input bit stream.

Claims

1. A method for recovering clock and data from an input bit stream, comprising:

receiving the input bit stream;

oversampling the received input bit stream using a plurality of phases of a reference clock signal to obtain one or more sets of data samples;

identifying one or more sets of non-transitioning phases of the one or more sets of data samples;

identifying one or more center phases corresponding to the one or more sets of non-transitioning phases, wherein a center phase corresponds to a set of non-transitioning phases;

calculating one or more bit-wise transition vectors corresponding to the identified one or more center phases;

comparing the one or more bit-wise transition vectors with one or more predefined bitmasks;

selecting a first final center phase from the identified one or more center phases based on the comparison of the bit-wise transition vectors with the one or more predefined bitmasks; and

recovering data by extracting data samples from the input bit stream corresponding to the selected first final center phase.

2. The method for recovering clock and data from an input bit stream of claim 1, wherein the one or more sets of non-transitioning phases are identified corresponding to data samples that do not switch between zero and one.

3. The method for recovering clock and data from an input bit stream method of claim 1, wherein the one or more bit-wise transition vectors are calculated based on transition of the data samples associated with the identified one or more center phases between zero and one.

4. The method for recovering clock and data from an input bit stream method of claim 1, wherein one or more center phases are determined based on a count of non-transitioning phases associated with the one or more sets of non-transitioning phases.

5. The method for recovering clock and data from an input bit stream of claim 4, further comprising selecting a second final center phase from the identified one or more center phases, based on the count of non-transitioning phases associated with the one or more sets of non-transitioning phases, wherein the second final center phase is selected based on the selection of the first final center phase.

6. The method for recovering clock and data from an input bit stream of claim 5, further comprising recovering data by extracting data samples corresponding to the selected second final center phase.

7. The method for recovering clock and data from an input bit stream of claim 1, further comprising identifying one or more final center phases selected in one or more previous clock and data recovery cycles.

8. The method for recovering clock and data from an input bit stream of claim 7, further comprising calculating an average center phase based on the identified one or more final center phases from previous clock and data recovery cycles.

9. The method for recovering clock and data from an input bit stream of claim 8, wherein the average center phase comprises at least one of a mean, a median, and a mode of the identified one or more final center phases from previous clock and data recovery cycles.

10. The method for recovering clock and data from an input bit stream of claim 9, further comprising selecting a set of non-transitioning phases from the identified one or more sets of non-transitioning phases of the current clock and data recovery cycle based on the calculated average center phase.

11. The method for recovering clock and data from an input bit stream of claim 10, further comprising selecting a third final center phase from the identified one or more center phases corresponding to the selected set of non-transitioning phases of current clock and data recovery cycle, wherein the third final center phase is selected based on selection of the second final center phase.

12. The method for recovering clock and data from an input bit stream of claim 11, further comprising recovering the clock and data by extracting data samples corresponding to the selected third final center phase.

13. The method for recovering clock and data from an input bit stream of claim 8, further comprising recovering the clock and data by extracting data samples corresponding to the average center phase.

14. A method for recovering clock and data from an input bit stream, comprising:

receiving the input bit stream;

oversampling the received input bit stream using a plurality of phases of a reference clock signal to obtain one or more sets of data samples, wherein each set of data samples corresponds to one bit width of received data of the received input bit stream, and wherein each set of data samples includes one of a received data bit and contiguous portions of more than one received data bit corresponding to one bit duration of the received data;

identifying one or more sets of non-transitioning phases corresponding to data samples that do not switch between zero and one;

identifying one or more center phases corresponding to the one or more sets of non-transitioning phases, wherein a center phase corresponds to a set of non-transitioning phases, and wherein each center phase is determined based on a count of non-transitioning phases associated with the one or more sets of non-transitioning phases;

identifying one or more final center phases selected in one or more previous clock and data recovery cycles;

calculating an average center phase based on the identified one or more final center phases in previous clock and data recovery cycles;

selecting a set of non-transitioning phases from the identified one or more sets of non-transitioning phases in the current clock and data recovery cycle based on the calculated average center phase;

selecting a first final center phase from the identified one or more center phases corresponding to the selected set of non-transitioning phases; and

recovering data by extracting data samples corresponding to the selected first final center phase.

15. The method for recovering clock and data from an input bit stream of claim 14, wherein the average center phase comprises at least one of a mean, a median, and a mode of the identified one or more final center phases.

16. The method for recovering clock and data from an input bit stream of claim 15, further comprising recovering data by extracting data samples corresponding to the calculated average center phase in previous clock and data recovery cycles.

17. A receiver system for recovering clock and data from an input bit stream, comprising:

a sampling unit for receiving the input bit stream and oversampling the received input bit stream using a plurality of phases of a reference clock signal to obtain one or more sets of data samples, wherein each set of data samples corresponds to one bit width of received data of the received input bit stream, and wherein each set of data samples comprises a received data bit or contiguous portions of more than one received data bit corresponding to one bit duration of the received data;

a serial to parallel data converter, connected to the sampling unit, for converting a serial stream of the one or more sets of data samples into one or more parallel streams of sets of data samples;

a clock and data recovery unit, connected to the serial to parallel data converter, for recovering clock and data from the one or more parallel streams of sets of data samples, wherein the clock and data recovery unit comprises;

a memory for storing the parallel streams of sets of data samples;

a non-transitioning phases identification unit, connected to the memory, for identifying one or more sets of non-transitioning phases corresponding to data samples that do not switch between zero and one;

a center phase identification unit, connected to the non-transitioning phases identification unit, for identifying one or more center phases corresponding to the one or more sets of non-transitioning phases, wherein a center phase corresponds to a set of non-transitioning phases, and wherein each of the identified one or more center phases is determined based on a count of non-transitioning phases associated with the identified one or more sets of non-transitioning phases;

a bit-wise transition vector calculation unit, connected to the center phase identification unit and the memory, for identifying one or more bit-wise transition vectors corresponding to the identified one or more center phases, based on switching of the data samples associated with the identified one or more center phases between zero and one;

a final center phase selection unit, connected to the bit-wise transition vector calculation unit, for selecting a final center phase from the identified one or more center phases for recovering data; and

a data recovery unit, connected to the final center phase selection unit and the memory, for recovering data by extracting data samples corresponding to the selected final center phase.

18. The receiver system of claim 17, wherein the clock and data recovery unit further comprises a glitch filter, connected to the memory, for eliminating glitches from the parallel streams of sets of data samples.

19. The receiver system of claim 17, wherein the clock and data recovery unit further comprises an elasticity buffer, connected to the data recovery unit, for maintaining synchronous data transmission between a transmitter system and the receiver system in a presence of a frequency drift.

20. The receiver system of claim 17, wherein the sampling unit further comprises a resynchronization unit for synchronizing sampling instants of the plurality of sets of data samples.