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Systems and methods for secure transaction management and electronic rights protection

  • US 8,181,021 B2
  • Filed: 08/20/2007
  • Issued: 05/15/2012
  • Est. Priority Date: 02/13/1995
  • Status: Expired due to Fees
First Claim
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1. An integrated circuit comprising:

  • a single silicon die, the single silicon die comprising;

    a first processing unit, the first processing unit comprisinga first microprocessor anda memory; and

    a first secure processing unit, communicatively coupled to the first processing unit, the first secure processing unit comprising;

    a second microprocessor,a first bus interface unit, the first bus interface unit being operable to restrict access to at least some components of the first secure processing unit by the first processing unit,random-access memory,non-volatile memory,a power failure sensing circuit, wherein the power failure sensing circuit is operable to render the non-volatile memory within the first secure processing unit resistant to tampering when a power failure is sensed, anda direct memory access controller.

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