System to improve error correction using variable latency and associated methods

• US 8,181,094 B2
• Filed: 01/31/2008
• Issued: 05/15/2012
• Est. Priority Date: 01/31/2008
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Lastras-Montano, Luis A., Patel, Piyush C., Retter, Eric E., Trager, Barry M., Trombley, Michael R., Winograd, Shmuel, Wright, Kenneth L.
• Primary Examiner(s): ABRAHAM, ESAW T
• Application Number:
  US12/023,546
• Publication Number:
  US 20100293438A1
• Time in Patent Office: 1,566 Days
• Field of Search: 714/763, 714/784, 714/785
• US Class Current: 714/776
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature

Abstract

A system to improve error correction includes a fast decoder to process data packets until the fast decoder finds an uncorrectable error in a data packet at which point a request for at least two data packets is generated. The system also includes a slow decoder to correct the uncorrectable error in a data packet based upon the at least two data packets.

Claims

1. A system to improve error correction using variable latency, the system comprising:

a first decoder to process data packets until said first decoder finds an uncorrectable error for a data packet at which point a request for at least two data packets is generated; and

a second decoder to correct the uncorrectable error in the data packet based upon the at least two data packets, the first decoder processes the data packets faster than the second decoder.

2. The system of claim 1 further comprising a memory to provide the at least two data packets based upon the request.

3. The system of claim 2 wherein said memory is partitioned into memory ranks comprised of memory chips.

4. The system of claim 3 wherein said second decoder examines the at least two data packets for failures to identify which memory chip contains the error that is uncorrectable by the first decoder.

5. The system of claim 1 wherein said second decoder uses a Chien search while processing the at least two data packets.

6. The system of claim 1 further comprising a table that contains information about persistent failures.

7. The system of claim 6 wherein said second decoder searches for new failures not already identified in said table that contains persistent failure information.

8. The system of claim 6 wherein said table is updated to contain information about correctable errors if said second decoder succeeds in locating any correctable errors.

9. The system of claim 1 wherein said second decoder processes each of the at least two data packets based upon computed syndromes for each of the at least two data packets.

10. The system of claim 9 wherein said second decoder processes the syndromes of the at least two data packets in parallel.

11. The system of claim 9 wherein said second decoder processes the syndromes of the at least two data packets serially.

12. The system of claim 9 wherein said second decoder receives one of the error packets syndromes as all zeros.

13. A method to improve error correction using variable latency, the method comprising:

processing data packets until a first decoder finds an uncorrectable error in a data packet at which point a request for at least two data packets is generated; and

correcting the uncorrectable error in the data packet via a second decoder using the at least two data packets, the first decoder processes the data packets faster than the second decoder.

14. The method of claim 13 wherein memory provides the at least two data packets based upon the request, and the memory is partitioned into memory ranks comprised of memory chips.

15. The method of claim 14 wherein the second decoder examines the at least two data packets for failures to identify which memory chip contains the uncorrectable error in the data packet.

16. The method of claim 13 wherein the second decoder processes each of the at least two data packets based upon computed syndromes for each of the at least two data packets.

17. A computer program product embodied in a non-transient tangible media comprising:

computer readable program codes coupled to the tangible media to improve error correction using variable latency, the computer readable program codes configured to cause the program to;

process data packets until a first decoder finds an uncorrectable error in a data packet at which point a request for at least two data packets is generated; and

correct the uncorrectable error in the data packet via a second decoder using the at least two data packets, the first decoder processes the data packets faster than the second decoder.

18. The computer program product of claim 17 further comprising program code configured to:

provide the at least two data packets based upon the request from memory that is partitioned into memory ranks and comprised of memory chips.

19. The computer program product of claim 18 further comprising program code configured to:

examine the at least two data packets for failures with the second decoder to identify which memory chip contains the error that is uncorrectable error by the first decoder.

20. The computer program product of claim 17 further comprising program code configured to:

process each of the at least two data packets with the second decoder based upon computed syndromes for each of the at least two data packets.