Semiconductor device and manufacturing method with improved epitaxial quality of III-V compound on silicon surfaces

• US 8,183,134 B2
• Filed: 01/19/2011
• Issued: 05/22/2012
• Est. Priority Date: 10/19/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Wu, Cheng-Hsien, Ko, Chih-Hsin, Wann, Clement Hsingjen
• Primary Examiner(s): SARKAR, ASOK K
• Application Number:
  US13/009,151
• Publication Number:
  US 20120094467A1
• Time in Patent Office: 489 Days
• Field of Search: 257/E21.118, 257/E21.127, 257/E21.449, 257/E21.451, 257/189, 257/200, 257/615, 357/E31.059, 438/22, 438/285, 438/478, 438/481, 438/604
• US Class Current: 438/481
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0243 Surface structure
• CPC Class Codes: H01L 21/02433 Crystal orientation
• CPC Class Codes: H01L 21/02538 Group 13/15 materials
• CPC Class Codes: H01L 21/02639 Preparation of substrate for selective deposition
• CPC Class Codes: H01L 21/02667 Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
• CPC Class Codes: H01L 21/02675 using laser beams
• CPC Class Codes: H01L 21/8258 the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213 , H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256

Abstract

Stacking faults are reduced or eliminated by epitaxially growing a III-V compound semiconductor region in a trench followed by capping and annealing the region. The capping layer limits the escape of atoms from the region and enables the reduction or elimination of stacking faults along with the annealing.

Claims

1. A method of forming a device, the method comprising:

providing a silicon substrate, wherein a major surface of the silicon substrate is a Si(001) surface, wherein the silicon substrate has insulation regions extending from the major surface into the silicon substrate, and wherein a portion of the silicon substrate is between opposite sidewalls of the insulation regions;

etching the portion of the silicon substrate to form a trench;

epitaxially growing a III-V compound semiconductor region in the trench;

depositing a capping layer on the silicon substrate to cover the III-V compound semiconductor region; and

annealing the silicon substrate after the depositing operation to reduce crystalline defects in the III-V compound semiconductor region.

2. The method of claim 1, wherein the trench has a bottom with a shape selected from a group consisting of V-shaped, U-shaped, and flat surface.

3. The method of claim 1, wherein a top surface of the silicon substrate exposed to the trench is a <

111>

surface with an off angle greater than about 6 degrees.

4. The method of claim 3, wherein a III-V crystalline compound in the III-V compound semiconductor region is deposited on the top surface, and wherein the <

111>

surface with an off angle greater than about 6 degrees of the top surface enables the epitaxially growing a III-V compound semiconductor region in the trench.

5. The method of claim 1, wherein the capping layer is a dielectric made of a material selected from a group consisting of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, and a low-dielectric-constant (low-K) dielectric.

6. The method of claim 1, wherein the capping layer is deposited by a process selected from a group consisting of plasma-enhanced chemical vapor deposition (PECVD), thermal chemical vapor deposition (CVD), and spin-on.

7. The method of claim 1, wherein the capping layer has a thickness in a range from about 20 nm to about 1000 nm.

8. The method of claim 1, wherein the capping layer and the annealing enable reducing crystalline defects.

9. The method of claim 1, wherein the annealing is performed by a process selected from a group consisting of rapid thermal annealing, laser anneal, flash anneal or furnace anneal.

10. The method of claim 1, wherein the annealing is performed for a duration in a range from about 10 μ

s to about 20 minutes.

11. The method of claim 1, wherein a III-V crystalline compound in the III-V semiconductor region is selected from a group consisting of GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlAs, AlP, GaP, or a combination thereof.

12. A method of forming a device, the method comprising:

providing a silicon substrate, wherein a major surface of the silicon substrate is a <

111>

surface with an off angle greater than about 6 degrees;

forming a trench on the silicon substrate, wherein the trench is between insulation regions extending from the major surface;

epitaxially growing a III-V compound semiconductor region in the trench;

depositing a capping layer on the silicon substrate to cover the III-V compound semiconductor region; and

annealing the silicon substrate after the depositing operation to reduce crystalline defects in the III-V compound semiconductor region.

13. The method of claim 12, wherein the insulation regions extend away from the major surface and are above the major surface.

14. The method of claim 12, wherein the insulation regions extend away from the major surface and are into the silicon substrate, and the trench is formed by etching the silicon substrate.

15. The method of claim 12, wherein a III-V crystalline compound in the III-V compound semiconductor region is grown on the major surface, and wherein the <

111>

surface with an off angle greater than about 6 degrees of the major surface enables the epitaxially growing the III-V crystalline compound.

16. The method of claim 12, wherein the capping layer is a dielectric made of a material selected from a group consisting of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, and a low-dielectric-constant (low-K) dielectric.

17. The method of claim 12, wherein the capping layer and the annealing enable reducing crystalline defects.

18. The method of claim 12, wherein the annealing is performed by a process selected from a group consisting of rapid thermal annealing, laser anneal, flash anneal or furnace anneal.