Reduced defectivity in contacts of a semiconductor device comprising replacement gate electrode structures by using an intermediate cap layer

• US 8,183,139 B2
• Filed: 12/09/2010
• Issued: 05/22/2012
• Est. Priority Date: 04/30/2010
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Marxsen, Gerd, Heinrich, Jens
• Primary Examiner(s): Coleman, William D
• Assistant Examiner(s): Enad, Christine
• Application Number:
  US12/963,908
• Publication Number:
  US 20110269303A1
• Time in Patent Office: 530 Days
• Field of Search: 438/586, 257/E21.19
• US Class Current: 438/586
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Abstract

Superior contact elements may be formed in semiconductor devices in which sophisticated replacement gate approaches may be applied. To this end, a dielectric cap layer is provided prior to patterning the interlayer dielectric material so that any previously created cracks may be reliably sealed prior to the deposition of the contact material, while the removal of any excess portion thereof may be performed without an undue interaction with the electrode metal of the gate electrode structures. Consequently, a significantly reduced defect rate may be achieved.

Claims

1. A method, comprising:

forming a dielectric cap layer above a gate electrode structure to fill at least one void in an interlayer dielectric material of a transistor formed above a semiconductor region, said gate electrode structure being laterally embedded in the interlayer dielectric material and comprising a high-k dielectric material and an electrode metal;

forming a contact opening laterally offset from said gate electrode structure so as to extend through said dielectric cap layer and said interlayer dielectric material;

forming a contact material in said contact opening;

removing an excess portion of said contact material so as to expose said dielectric cap layer; and

performing a removal process to remove a first portion of the dielectric cap layer so as to expose said electrode metal of said gate electrode structure and leave a second portion of the dielectric cap layer in said at least one void.

2. The method of claim 1, wherein removing an excess portion of said contact material comprises performing a chemical mechanical polishing process.

3. The method of claim 1, wherein performing said removal process comprises performing a polishing process.

4. The method of claim 1, wherein performing said removal process comprises performing an etch process.

5. The method of claim 1, further comprising forming said gate electrode structure by providing said gate electrode structure so as to comprise a placeholder material, removing said placeholder material, forming at least said electrode metal and removing an excess portion of said electrode metal by performing a chemical mechanical polishing process.

6. The method of claim 1, wherein forming said contact opening comprises patterning said dielectric cap layer and using said patterned dielectric cap layer as an etch mask.

7. The method of claim 1, wherein said electrode metal and said contact material have different material compositions.

8. The method of claim 1, wherein removing an excess portion of said contact material and exposing said electrode metal comprises performing a single chemical mechanical polishing process.

9. The method of claim 1, wherein a lateral distance between said electrode metal and said contact material is 40 nm or less after performing said removal process.

10. A method, comprising:

forming an electrode metal in an opening of a gate electrode structure of a transistor, said gate electrode structure being laterally embedded in a dielectric material;

removing an excess portion of said electrode metal by performing a first removal process;

forming a dielectric cap layer above said electrode metal and said dielectric material to fill at least one void in said dielectric material;

forming a contact opening in said dielectric cap layer and said dielectric material without exposing said electrode metal, said contact opening connecting to one of a drain region and a source region;

forming a contact metal in said contact opening and above said dielectric cap layer;

removing an excess portion of said contact metal by performing a second removal process; and

exposing said electrode metal by removing a first portion of the dielectric cap layer, wherein a second portion of the dielectric cap layer remains in said at least one void.

11. The method of claim 10, wherein performing said first removal process comprises performing a first chemical mechanical polishing process.

12. The method of claim 11, wherein performing said second removal process comprises performing a second chemical mechanical polishing process.

13. The method of claim 10, wherein exposing said electrode metal comprises exposing said electrode metal after performing said second removal process.

14. The method of claim 13, wherein exposing said electrode metal comprises performing a polishing process.

15. The method of claim 13, wherein exposing said electrode metal comprises performing an etch process.

16. The method of claim 10, wherein forming said contact opening comprises forming a mask opening in said dielectric cap layer and using said mask opening as an etch mask.

17. The method of claim 10, wherein a lateral offset of said contact opening from said electrode metal is 40 nm or less.

18. A method, comprising:

forming a dielectric cap layer above a gate electrode structure to fill at least one void in an interlayer dielectric material of a transistor formed above a semiconductor region, said gate electrode structure being laterally embedded in the interlayer dielectric material and comprising a high-k dielectric material and an electrode metal; and

performing a removal process to remove a first portion of the dielectric cap layer so as to expose said electrode metal of said gate electrode structure and leave a second portion of the dielectric cap layer in said at least one void.

19. The method of claim 18, comprising forming a contact opening laterally offset from said gate electrode structure so as to extend through said dielectric cap layer and said interlayer dielectric material and forming a contact material in said contact opening.

20. The method of claim 19, comprising removing an excess portion of said contact material so as to expose said dielectric cap layer.