Semiconductor device having silicon carbide and conductive pathway interface

• US 8,183,150 B2
• Filed: 10/24/2008
• Issued: 05/22/2012
• Est. Priority Date: 11/17/1998
• Status: Expired due to Fees

• Current Assignee: Applied Materials Incorporated
• Original Assignee: Applied Materials Incorporated
• Inventors: Huang, Judy H., Bencher, Christopher Dennis, Rathi, Sudha, Ngai, Christopher S., Kim, Bok Hoen
• Primary Examiner(s): Nguyen, Ha Tran T
• Assistant Examiner(s): Tran, Thanh Y
• Application Number:
  US12/257,806
• Publication Number:
  US 20090050902A1
• Time in Patent Office: 1,306 Days
• Field of Search: 438/629, 438/637, 438/639, 438/640, 438/667, 438/668, 438/672, 438/675, 438/700, 438/701, 438/713, 438/622, 438/625, 438/626, 438/627, 438/635, 438/638, 438/671, 438/118, 438/878, 438/643, 438/653, 438/927, 438/687, 438/683, 438/685, 257/774, 257/E23.001, 257/E23.142, 257/E23.145, 257/775, 257/E21.585, 257/758, 257/751, 257/762, 257/763
• US Class Current: 438/627
• CPC Class Codes: B08B 7/0035 by radiant energy, e.g. UV, laser, light beam or the like
• CPC Class Codes: C23C 16/0245 by etching with a plasma
• CPC Class Codes: C23G 5/00 Cleaning or de-greasing metallic material by other methods; Apparatus for cleaning or de-greasing metallic material with organic solvents
• CPC Class Codes: H01L 21/02063 the processing being the formation of vias or contact holes
• CPC Class Codes: H01L 21/02068 during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
• CPC Class Codes: H01L 21/02071 the processing being a delineation, e.g. RIE, of conductive layers
• CPC Class Codes: H01L 21/02074 the processing being a planarization of conductive layers
• CPC Class Codes: H01L 21/02115 the material being carbon, e.g. alpha-C, diamond or hydrogen doped carbon
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/02167 the material being a silicon carbide not containing oxygen, e.g. SiC, SiC:H or silicon carbonitrides H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/02211 the compound being a silane, e.g. disilane, methylsilane or chlorosilane
• CPC Class Codes: H01L 21/02274 in the presence of a plasma [PECVD]
• CPC Class Codes: H01L 21/0234 treatment by exposure to a plasma
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/3148 Silicon Carbide layers
• CPC Class Codes: H01L 21/3185 of siliconnitrides
• CPC Class Codes: H01L 21/32136 using plasmas
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76877 : Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76883 : Post-treatment or after-treatment of the conductive material
• CPC Class Codes: H01L 23/53238 : Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

The present invention provides semiconductor device formed by an in situ plasma reducing process to reduce oxides or other contaminants, using a compound of nitrogen and hydrogen, typically ammonia, at relatively low temperatures prior to depositing a subsequent layer thereon. The adhesion characteristics of the layers are improved and oxygen presence is reduced compared to the typical physical sputter cleaning process of an oxide layer. This process may be particularly useful for the complex requirements of a dual damascene structure, especially with copper applications.

Claims

1. A method for forming a semiconductor device, comprising:

forming an interface defined by a first insulating layer comprising silicon carbide and one or more conductive pathways disposed within the first insulating layer, portions of the one or more conductive pathways of the interface having oxidation disposed thereon;

plasma treating the interface by a gas mixture consisting of NH₃ to remove the oxidation from the interface, wherein plasma treating comprises providing a plurality of NH₃ treatment cycles separated by a purge cycle; and

in-situ depositing a second insulating layer on the interface concurrently with the removal of the oxidation from the interface.

2. The method of claim 1 wherein the conductive pathways are formed from at least one of copper, titanium, tantalum, and tungsten.

3. The method of claim 1, wherein the second insulating layer comprises at least one layer selected from the group consisting of a patterned etch stop layer, a barrier layer, and a film comprising silicon carbide.

4. The method of claim 1, wherein in-situ depositing the second insulating layer on the interface comprises depositing the second insulating layer directly on the conductive pathways.

5. A method for forming a semiconductor device, comprising:

forming an interface defined by a first insulating layer and one or more conductive pathways disposed within said first insulating layer, the interface having oxidation reduced portions; and

depositing a second insulating layer disposed upon said interface coincident with removal of said oxidation reduced portions by a plasma treatment process formed from a gas mixture consisting of NH₃ gas, wherein the plasma treatment process comprises providing a plurality of NH₃ treatment cycles separated by a purge cycle.

6. The method of claim 5 wherein the first insulating layer is selected from a group consisting of at least one of oxides and nitrides.

7. The method of claim 5 wherein the conductive pathways comprise metals selected from a group consisting of at least one of titanium, tantalum, tungsten and copper.

8. The method semiconductor device of claim 5 wherein the second insulating layer is selected from a group consisting of at least one of oxides and nitrides.

9. The method of claim 5, wherein depositing the second insulating layer on the interface comprises depositing the second insulating layer directly on the conductive pathways.

10. A method for forming a semiconductor device, comprising:

forming an interface defined by a first insulating layer comprising silicon carbide and one or more conductive pathways disposed within the first insulating layer, exposed surfaces of the one or more conductive pathways of the interface having oxidation disposed thereon;

plasma treating the interface to remove the oxidation from the interface, wherein plasma treating comprises providing a plurality of NH₃ treatment cycles separated by a purge cycle; and

in-situ depositing a second insulating layer directly on the exposed surfaces of the conductive pathways on the interface concurrently with the removal of the oxidation from the interface.

11. The method of claim 10, wherein the plasma treatment further comprises:

forming a plasma from a gas mixture including NH₃.

12. The method of claim 11 wherein the conductive pathways are formed from at least one of copper, titanium, tantalum, and tungsten.

13. The method of claim 11, wherein the second insulating layer comprises at least one layer selected from the group consisting of a patterned etch stop layer, a barrier layer, and a film comprising silicon carbide.

14. The method of claim 11 wherein the first insulating layer is selected from a group consisting of at least one of oxides and nitrides.

15. The method of claim 14 wherein the conductive pathways comprise copper.

16. The method of claim 10, wherein in-situ depositing the second insulating layer on the interface comprises depositing the second insulating layer directly on the conductive pathways.