Hybrid fin field-effect transistor structures and related methods

• US 8,183,627 B2
• Filed: 05/22/2008
• Issued: 05/22/2012
• Est. Priority Date: 12/01/2004
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Currie, Matthew T.
• Primary Examiner(s): Vu, Hung
• Application Number:
  US12/125,308
• Publication Number:
  US 20080265280A1
• Time in Patent Office: 1,461 Days
• Field of Search: 257/329, 257/401, 257/618, 257/619, 257/623, 257/E21.442, 257/E29.275
• US Class Current: 257/329
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7849 the means being provided under the channel
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78681 having a semiconductor body comprising AIIIBV or AIIBVI or AIVBVI semiconductor materials, or Se or Te
• CPC Class Codes: H01L 29/78687 with a multilayer structure or superlattice structure

Abstract

Semiconductor-on-insulator structures facilitate the fabrication of devices, including MOSFETs that are at least partially depleted during operation and FinFETs including bilayer fins and/or crystalline oxide.

Claims

1. A structure comprising:

a substrate having an insulator layer disposed thereon; and

a fin field-effect transistor disposed over the substrate, the fin field-effect transistor including;

a source region and a drain region disposed in contact with the insulator layer;

at least one fin extending between the source and the drain regions and comprising a bilayer;

a gate disposed above the bilayer, extending over the at least one fin and between the source and the drain regions; and

a gate dielectric layer disposed between the gate and the fin,

wherein the bilayer comprises a second semiconductor material disposed over a first semiconductor material, and the first semiconductor material is different from the second semiconductor material, and a sidewall surface of the at least one fin includes the first semiconductor material.

2. The structure of claim 1, wherein the first semiconductor material includes at least one member of the group consisting of silicon, SiGe, germanium, an array of carbon nanotubes, and mixtures or alloys thereof.

3. The structure of claim 1, wherein the first semiconductor material includes at least one member of the group consisting of gallium arsenide, indium arsenide, indium gallium arsenide, indium phosphide, gallium nitride, indium antimonide, gallium antimonide, gallium phosphide, and mixtures or alloys thereof.

4. The structure of claim 1, wherein the second semiconductor material includes at least one member of the group consisting of silicon, SiGe, germanium, an array of carbon nanotubes, and mixtures or alloys thereof.

5. The structure of claim 1, wherein the second semiconductor material includes at least one member of the group consisting of gallium arsenide, indium arsenide, indium gallium arsenide, indium phosphide, gallium nitride, indium antimonide, gallium antimonide, gallium phosphide, and mixtures or alloys thereof.

6. The structure of claim 1, wherein the first semiconductor material is tensilely strained and the second semiconductor material is compressively strained.

7. The structure of claim 1, wherein the first semiconductor material is compressively strained and the second semiconductor material is tensilely strained.

8. The structure of claim 1, wherein the gate dielectric is disposed proximate the first semiconductor material and the second semiconductor material.

9. A structure comprising:

a substrate;

a first crystalline insulator layer disposed over at least a first portion of the substrate;

a second crystalline insulator layer disposed over at least a second portion of the substrate;

a first fin field-effect transistor disposed over the substrate, the first fin field-effect-transistor including;

a first source region and a first drain region disposed over and in contact with the first crystalline insulator layer;

a first fin extending between the first source and the first drain regions, the first fin comprising a first semiconductor material disposed on at least one vertically oriented sidewall of the first fin;

a first gate, disposed above the substrate, extending over the first fin and between the first source and the first drain regions;

a first gate dielectric layer disposed between the first gate and the first fin; and

a second fin field-effect transistor disposed over the substrate, the second fin field-effect-transistor including;

a second source region and a second drain region disposed over and in contact with the second crystalline insulator layer;

a second fin extending between the second source and the second drain regions and comprising a second semiconductor material disposed on at least one vertically oriented sidewall of the second fin;

a second gate, disposed above the substrate, extending over the second fin and between the second source and the second drain regions; and

a second gate dielectric layer disposed between the second gate and the second fin,

wherein the first semiconductor material has a first crystalline orientation, the second semiconductor material has a second crystalline orientation, and the first and second crystalline orientations are different.

10. The structure of claim 9, wherein the first fin and second fin are substantially parallel.

11. The structure of claim 9, wherein the first semiconductor material and the second semiconductor material are substantially the same.

12. The structure of claim 9, wherein the first crystalline orientation is selected from a {100} family of crystalline planes.

13. The structure of claim 9, wherein the first crystalline orientation is selected from a {110} family of crystalline planes.

14. The structure of claim 9, wherein the first fin field-effect transistor comprises an n-channel device and the second fin field-effect transistor comprises a p-channel device.

15. A structure comprising:

a substrate;

a crystalline insulator material disposed over the substrate;

a first fin field-effect transistor disposed over the substrate; and

a second fin field-effect transistor disposed over the substrate, at least one of the first fin field-effect transistor or the second field-effect transistor being disposed over the crystalline insulator material;

wherein the first fin field-effect transistor comprises a first semiconductor material has a first crystalline orientation, the second fin field-effect transistor comprises a second semiconductor material has a second crystalline orientation, and the first and second crystalline orientations are different.