Stacked trench metal-oxide-semiconductor field effect transistor device
First Claim
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1. An integrated circuit comprising:
- a drain-side-gate trench metal-oxide-semiconductor field effect transistor including;
a source region;
a plurality of gate regions disposed above said source region, wherein said plurality of gate regions are formed as substantially parallel elongated structure;
a plurality of gate insulator regions, wherein each of said plurality of gate insulator regions are disposed about a periphery of a respective one of said plurality of gate regions;
a plurality of body regions disposed above said source region and between said plurality of gate insulator regions;
a plurality of source-body contacts disposed between and electrically coupled to said source region and said plurality of body regions;
a plurality of drift regions disposed above said plurality of body regions and between said plurality of gate insulator regions; and
a plurality of drain regions disposed above said plurality of drift regions and between said plurality of gate insulator regions;
a source-side-gate trench metal-oxide-semiconductor field effect transistor; and
a metal lead coupling a drain of said source-side-gate trench metal-oxide-semiconductor field effect transistor to a source of said drain-side-gate trench metal-oxide-semiconductor field effect transistor.
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Abstract
Embodiments of the present invention are directed toward a trench metal-oxide-semiconductor field effect transistor (TMOSFET) device. The TMOSFET device includes a source-side-gate TMOSFET coupled to a drain-side-gate TMOSFET 1203. A switching node metal layer couples the drain of the source-side-gate TMOSFET to the source of the drain-side-gate TMOSFET so that the TMOSFETs are packaged as a stacked or lateral device.
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Citations
10 Claims
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1. An integrated circuit comprising:
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a drain-side-gate trench metal-oxide-semiconductor field effect transistor including; a source region; a plurality of gate regions disposed above said source region, wherein said plurality of gate regions are formed as substantially parallel elongated structure; a plurality of gate insulator regions, wherein each of said plurality of gate insulator regions are disposed about a periphery of a respective one of said plurality of gate regions; a plurality of body regions disposed above said source region and between said plurality of gate insulator regions; a plurality of source-body contacts disposed between and electrically coupled to said source region and said plurality of body regions; a plurality of drift regions disposed above said plurality of body regions and between said plurality of gate insulator regions; and a plurality of drain regions disposed above said plurality of drift regions and between said plurality of gate insulator regions; a source-side-gate trench metal-oxide-semiconductor field effect transistor; and a metal lead coupling a drain of said source-side-gate trench metal-oxide-semiconductor field effect transistor to a source of said drain-side-gate trench metal-oxide-semiconductor field effect transistor. - View Dependent Claims (2, 3, 4)
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5. A stacked trench metal-oxide-semiconductor field effect transistor device comprising:
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a first drain; a first gate disposed below said first drain; a first gate insulator disposed about a periphery of said first gate; a first body disposed below said first drain and between said first gate insulator; a first source disposed between said first body and said first gate insulator, wherein said first source is separated from said first drain by said first body; a switching node layer disposed above said first drain; a second source disposed above said switching node; a second gate disposed above said second source; a second gate insulator is disposed about a periphery of said second gate; a second body disposed above said second source and between said second gate insulator; a second drift disposed above said second body and between said second gate insulator; and a second drain disposed above said second drift and between said second gate insulator. - View Dependent Claims (6, 7)
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8. An integrated circuit comprising:
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a drain-side-gate trench metal-oxide-semiconductor field effect transistor including; a source region; a gate region disposed above said source region, wherein a first portion of said plurality of gate regions are formed as substantially parallel elongated structures and a second portion of said plurality of gate regions are formed as substantially normal-to-parallel elongated structures; a gate insulator region, wherein said gate insulator region is disposed about a periphery of said gate region; a plurality of body regions disposed above said source region and between said gate insulator region; a plurality of first source-body contacts electrically coupled to said plurality of body regions; a plurality of second source-body contacts electrically coupled between said plurality of first source-body contacts and said source region; and a plurality of source-body contact insulator regions for electrically isolating said plurality of first source-body contacts and said plurality of second source-body contacts from one or more of said plurality of drift regions and said plurality of drain regions a plurality of drift regions disposed above said plurality of body regions and between said gate insulator region; a plurality of drain regions disposed above said plurality of drift regions and between said gate insulator regions; and a plurality of source-body contact insulator regions for electrically isolating said plurality of first source-body contacts and said plurality of second source-body contacts from one or more of said plurality of drift regions and said plurality of drain regions a source-side-gate trench metal-oxide-semiconductor field effect transistor; and a metal lead coupling a drain of said source-side-gate trench metal-oxide-semiconductor field effect transistor to a source of said drain-side-gate trench metal-oxide-semiconductor field effect transistor. - View Dependent Claims (9, 10)
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Specification