Stacked trench metal-oxide-semiconductor field effect transistor device

• US 8,183,629 B2
• Filed: 03/18/2008
• Issued: 05/22/2012
• Est. Priority Date: 05/13/2004
• Status: Active Grant

• Current Assignee: Vishay Siliconix
• Original Assignee: Vishay Siliconix
• Inventors: Pattanayak, Deva, Qi, Jason (Jianhai), Bai, Yuming, Lui, Kam-Hong, Wong, Ronald
• Primary Examiner(s): ARMAND, MARC ANTHONY
• Application Number:
  US12/050,929
• Publication Number:
  US 20090050960A1
• Time in Patent Office: 1,526 Days
• Field of Search: 257/334, 257/E27.06, 257/330, 257/328, 257/331, 257/332, 257/369, 257/333
• US Class Current: 257/334
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/781 Inverted VDMOS transistors, i.e. Source-Down VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

Embodiments of the present invention are directed toward a trench metal-oxide-semiconductor field effect transistor (TMOSFET) device. The TMOSFET device includes a source-side-gate TMOSFET coupled to a drain-side-gate TMOSFET 1203. A switching node metal layer couples the drain of the source-side-gate TMOSFET to the source of the drain-side-gate TMOSFET so that the TMOSFETs are packaged as a stacked or lateral device.

Claims

1. An integrated circuit comprising:

a drain-side-gate trench metal-oxide-semiconductor field effect transistor including;

a source region;

a plurality of gate regions disposed above said source region, wherein said plurality of gate regions are formed as substantially parallel elongated structure;

a plurality of gate insulator regions, wherein each of said plurality of gate insulator regions are disposed about a periphery of a respective one of said plurality of gate regions;

a plurality of body regions disposed above said source region and between said plurality of gate insulator regions;

a plurality of source-body contacts disposed between and electrically coupled to said source region and said plurality of body regions;

a plurality of drift regions disposed above said plurality of body regions and between said plurality of gate insulator regions; and

a plurality of drain regions disposed above said plurality of drift regions and between said plurality of gate insulator regions;

a source-side-gate trench metal-oxide-semiconductor field effect transistor; and

a metal lead coupling a drain of said source-side-gate trench metal-oxide-semiconductor field effect transistor to a source of said drain-side-gate trench metal-oxide-semiconductor field effect transistor.

2. The integrated circuit of claim 1, wherein:

said source region comprises a heavily n-doped semiconductor;

said plurality of body regions comprise a p-doped semiconductor;

said plurality of drift regions comprise a lightly n-doped semiconductor;

said plurality of drain regions comprise a heavily n-doped semiconductor;

said plurality of gate insulator regions comprise an oxide; and

said plurality of gate regions comprise a heavily n-doped semiconductor.

3. The integrated circuit of claim 1, wherein said drain-side-gate trench metal-oxide-semiconductor field effect transistor further comprises:

wherein said plurality of source-body contacts include a plurality of first source-body contacts electrically coupled to said plurality of body regions;

wherein said plurality of source-body contacts further include a plurality of second source-body contacts electrically coupled between said plurality of first source-body contacts and said source region; and

a source-body contact insulator region for electrically isolating said first source-body contact and said second source-body contact from one or more of said plurality of drift regions and said plurality of drain regions.

4. The integrated circuit of claim 3, wherein:

said plurality of first source-body contacts comprise a heavily p-doped semiconductor; and

said plurality of second source-body contacts comprise a silicide.

5. A stacked trench metal-oxide-semiconductor field effect transistor device comprising:

a first drain;

a first gate disposed below said first drain;

a first gate insulator disposed about a periphery of said first gate;

a first body disposed below said first drain and between said first gate insulator;

a first source disposed between said first body and said first gate insulator, wherein said first source is separated from said first drain by said first body;

a switching node layer disposed above said first drain;

a second source disposed above said switching node;

a second gate disposed above said second source;

a second gate insulator is disposed about a periphery of said second gate;

a second body disposed above said second source and between said second gate insulator;

a second drift disposed above said second body and between said second gate insulator; and

a second drain disposed above said second drift and between said second gate insulator.

6. The stacked trench metal-oxide-semiconductor field effect transistor device according to claim 5, wherein said first and second gates are each formed as substantially parallel elongated structures.

7. The stacked trench metal-oxide-semiconductor field effect transistor device according to claim 5, wherein:

a first portion of said first gate is formed as substantially parallel elongated structures and a second portion of said first gate is formed as substantially normal-to-parallel elongated structures; and

a first portion of said second gate is formed as substantially parallel elongated structures and a second portion of the second gate is formed as substantially normal-to-parallel elongated structures.

8. An integrated circuit comprising:

a drain-side-gate trench metal-oxide-semiconductor field effect transistor including;

a source region;

a gate region disposed above said source region, wherein a first portion of said plurality of gate regions are formed as substantially parallel elongated structures and a second portion of said plurality of gate regions are formed as substantially normal-to-parallel elongated structures;

a gate insulator region, wherein said gate insulator region is disposed about a periphery of said gate region;

a plurality of body regions disposed above said source region and between said gate insulator region;

a plurality of first source-body contacts electrically coupled to said plurality of body regions;

a plurality of second source-body contacts electrically coupled between said plurality of first source-body contacts and said source region; and

a plurality of source-body contact insulator regions for electrically isolating said plurality of first source-body contacts and said plurality of second source-body contacts from one or more of said plurality of drift regions and said plurality of drain regions

a plurality of drift regions disposed above said plurality of body regions and between said gate insulator region;

a plurality of drain regions disposed above said plurality of drift regions and between said gate insulator regions; and

a plurality of source-body contact insulator regions for electrically isolating said plurality of first source-body contacts and said plurality of second source-body contacts from one or more of said plurality of drift regions and said plurality of drain regions

a source-side-gate trench metal-oxide-semiconductor field effect transistor; and

a metal lead coupling a drain of said source-side-gate trench metal-oxide-semiconductor field effect transistor to a source of said drain-side-gate trench metal-oxide-semiconductor field effect transistor.

9. The integrated circuit of claim 8, wherein:

said source region comprises a heavily n-doped semiconductor;

said plurality of body regions comprise a p-doped semiconductor;

said plurality of drift regions comprise a lightly n-doped semiconductor;

said plurality of drain regions comprise a heavily n-doped semiconductor;

said gate insulator region comprises an oxide; and

said gate region comprises a heavily n-doped semiconductor.

10. The integrated circuit of claim 8, wherein:

said plurality of first source-body contacts comprise a heavily p-doped semiconductor; and

said plurality of second source-body contacts comprise a silicide.