Circuit with transistors integrated in three dimensions and having a dynamically adjustable threshold voltage VT

• US 8,183,630 B2
• Filed: 05/29/2009
• Issued: 05/22/2012
• Est. Priority Date: 06/02/2008
• Status: Active Grant

• Current Assignee: Commissariat a L'Energie Atomique (AES Corporation)
• Original Assignee: Commissariat a L'Energie Atomique (AES Corporation)
• Inventors: Batude, Perrine, Clavelier, Laurent, Jaud, Marie-Anne, Thomas, Olivier, Vinet, Maud
• Primary Examiner(s): Matthews, Collen A
• Assistant Examiner(s): Yushina, Galina
• Application Number:
  US12/474,851
• Publication Number:
  US 20090294822A1
• Time in Patent Office: 1,089 Days
• Field of Search: 257/E21.614, 257/E27.098, 257/296, 257/E21.661, 257/E21.613, 257/E27.077, 257/310, 257/337
• US Class Current: 257/337
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element
• CPC Class Codes: H10B 10/125 the MOSFET being a thin film transistor [TFT]

Abstract

A microelectronic device including: a substrate surmounted by a stack of layers, at least one first transistor situated at a given level of said stack, at least one second transistor situated at a second level of said stack, above said given level, the first transistor including a gate electrode situated opposite a channel zone of the second transistor, the first transistor and the second transistor being separated by an insulating zone, and said insulating zone being constituted of several different dielectric materials include a first dielectric material and a second dielectric material.

Claims

1. A microelectronic device comprising:

a substrate surmounted by a stack of layers,

at least one first transistor situated at a given level of said stack,

at least one second transistor situated at a second level of said stack, above said given level, the first transistor comprising a gate electrode situated opposite a channel zone of the second transistor, the first transistor and the second transistor being separated by an insulating zone,

said insulating zone being constituted of several different dielectric materials including a first dielectric material and a second dielectric material, and having in a first region extending from a top surface of said gate electrode of said first transistor to a bottom surface of said channel of said second transistor, a composition and a thickness provided so as to form a first electric capacitance C1 between the gate electrode of the first transistor and the channel of the second transistor, said first region only including the first dielectric material, said insulating zone comprising a second region that includes the second dielectric material extending from a bottom of the channel of the second transistor to a top surface of at least one access zone of the first transistor and having a thickness so as to form a second electric capacitance C2 between said access zone of the first transistor an access zone of the second transistor, such that C2<

C1.

2. The microelectronic device according to claim 1, wherein said first region is formed only of the first dielectric material having a first dielectric constant k₁, and the second region is formed of the second dielectric material having a second dielectric constant k₂ such that k₂<

k₁.

3. The microelectronic device according to claim 1, wherein said first region of the insulating zone has an equivalent SiO₂ thickness between 1 and 50 nanometres.

4. The microelectronic device according to claim 1, wherein a channel zone of the first transistor is situated fully opposite a gate electrode of the second transistor.

5. The microelectronic device according to claim 1, further comprising, in an axis orthogonal to a principal plane of the substrate passing through the gate electrode of the first transistor and the second transistor, one or several other transistors.

6. The microelectronic device according to claim 1, further comprising:

at least one third transistor situated at the level of said first transistor in said stack, and

at least one fourth transistor situated above the third transistor, the fourth transistor and the third transistor being separated by a dielectric zone provided to limit or prevent a coupling between the third transistor and the fourth transistor.

7. The microelectronic device according to claim 1, further comprising:

at least one third transistor situated at the level of said first transistor in said stack,

at least one fourth transistor, and

a fifth decoupling transistor situated between the third transistor and the fourth transistor.

8. The device according to claim 1, further comprising:

one or several other transistors in a plane parallel to a principal plane of the substrate and passing through at least one of the gate electrode of the first transistor and a gate electrode of the second transistor.

9. The microelectronic device according to claim 1, further comprising at least one contact pad between the gate electrode of the first transistor and a gate electrode of the second transistor.

10. The microelectronic device according to claim 1, wherein the transistors belong to a SRAM memory cell.

11. The microelectronic device according to claim 1, wherein the first region has width equal to a width of the gate electrode of the first transistor.

12. The microelectronic device according to claim 1, further comprising:

means for modulating a threshold voltage of the second transistor, including means for applying a variable potential to said gate electrode of said first transistor and

to apply to the gate electrode of the first transistor, during a first phase, at least one first potential, and

to apply to the gate electrode of the first transistor, during a second phase, at least one second potential, different from said first potential.

13. The microelectronic device according to claim 12, wherein said first potential is provided to turn on said second transistor and impose a first threshold voltage on the second transistor, and said second potential is provided to turn off said second transistor and impose a second threshold voltage, greater than said first threshold voltage.

14. The microelectronic device according to claim 1, wherein said insulating zone has in the first region a composition and a thickness that enables a coupling between the gate electrode of the first transistor and the channel of the second transistor.

15. The microelectronic device according to claim 14, wherein said insulating zone has, in the second region between said access zone of said first transistor and said access zone of said second transistor, a composition and a thickness that limits or prevents a coupling between said access zone of the first transistor and said access zone of the second transistor.

16. The microelectronic device according to claim 14, wherein the coupling between the gate electrode of the first transistor and the channel of the second transistor is such that a variation in gate potential of the first transistor brings a variation in threshold voltage of the second transistor.

17. The microelectronic device according to claim 16, wherein Vdd is a supply voltage of the microelectronic device, and the coupling between the gate electrode of the first transistor and the channel of the second transistor is such that a variation in the gate potential of the first transistor obtains the variation in the threshold voltage of the second transistor of at least 50 mV.

18. The microelectronic device according to claim 17, wherein said gate potential varies between 0 and Vdd or between −

Vdd and +Vdd.

19. A microelectronic device comprising:

a substrate surmounted by a stack of layers,

at least one first transistor situated at a given level of said stack,

at least one second transistor situated at a second level of said stack, above said given level, the first transistor comprising a gate electrode situated opposite a channel zone of the second transistor, the first transistor and the second transistor being separated by an insulating zone,

said insulating zone being constituted of several different dielectric materials including a first dielectric material and a second dielectric material, and having in a first region extending from a top surface of said gate electrode of said first transistor to a bottom surface of said channel of said second transistor, a composition and a thickness provided so as to form a first electric capacitance C1 between the gate electrode of the first transistor and the channel of the second transistor, said first region is formed only of the first dielectric material having a first dielectric constant k₁, said insulating zone comprising a second region that extends from a bottom of the channel of the second transistor to a top surface of at least one access zone of the first transistor and that includes a stack of the first dielectric material and the second dielectric material having a second dielectric constant k₂ such that k₂<

k₁, the second region having a thickness so as to form a second electric capacitance C2 between said access zone of the first transistor and an access zone of the second transistor, such that C2<

C1.