Field effect transistor with narrow bandgap source and drain regions and method of fabrication

• US 8,183,646 B2
• Filed: 02/04/2011
• Issued: 05/22/2012
• Est. Priority Date: 02/23/2005
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Chau, Robert S., Datta, Suman, Kavalieros, Jack, Brask, Justin K., Doczy, Mark L., Metz, Matthew
• Primary Examiner(s): Valentine, Jami M
• Application Number:
  US13/021,640
• Publication Number:
  US 20110121393A1
• Time in Patent Office: 473 Days
• Field of Search: 257/300, 257/615, 257/368, 257/288, 257/213, 257/613, 438/197, 438/478
• US Class Current: 257/401
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/20 including, apart from doping materials or other impurities, only AIIIBV compounds
• CPC Class Codes: H01L 29/201 including two or more compounds , e.g. alloys H01L29/2006 takes precedence
• CPC Class Codes: H01L 29/207 further characterised by the doping material H01L29/2006 takes precedence
• CPC Class Codes: H01L 29/267 in different semiconductor regions , e.g. heterojunctions H01L29/263 takes precedence
• CPC Class Codes: H01L 29/41783 Raised source or drain electrodes self aligned with the gate
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/452 on AIII-BV compounds
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66522 with an active layer made of a group 13/15 material H01L29/66446 takes precedence
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7836 with a significant overlap between the lightly doped extension and the gate electrode H01L29/7834, H01L29/7835 take precedence
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 : having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78603 : characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/78618 : characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78681 : having a semiconductor body comprising AIIIBV or AIIBVI or AIVBVI semiconductor materials, or Se or Te

Abstract

A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.

Claims

1. A transistor comprising:

a gate dielectric layer formed on a silicon-on-insulator (SOI) substrate;

a gate electrode formed on the gate dielectric layer; and

a pair of source/drain regions on opposite sides of the gate electrode, the pair of source/drain regions comprising a doped semiconductor film directly beneath the gate electrode, wherein the semiconductor film has a bandgap of less than 0.75 eV;

wherein the semiconductor film is either;

doped to an n type conductivity with a dopant selected from the group consisting of tellurium (Te), silicon (Si) and sulfur (S);

or

doped to a p type conductivity with a dopant selected from the group consisting of carbon (C), cadmium (Cd), zinc (Zn) and chromium (Cr).

2. The transistor of claim 1 wherein the semiconductor film is selected from the group consisting of indium antimonide (InSb), indium arsenide (InAs), indium gallium arsenide (In_1-xGa_xAs(x>

50%)) and indium phosphide (InP).

3. The transistor of claim 1 wherein the semiconductor film is indium phosphide (InP).

7. The transistor of claim 1 wherein the semiconductor film is doped to the n type conductivity with a dopant selected from the group consisting of tellurium (Te), silicon (Si) and sulfur (S).

11. The transistor of claim 1 wherein the semiconductor film is doped to the p type conductivity with a dopant selected from the group consisting of carbon (C), cadmium (Cd), zinc (Zn) and chromium (Cr).

12. The transistor of claim 3 further comprising a pair of non-alloyed contacts on the indium phosphide (InP) film.

13. The transistor of claim 12 wherein the non-alloyed contacts comprise a bi-layer of titanium/gold.

4. A transistor comprising:

a gate dielectric layer formed on a silicon-on-insulator (SOI) substrate;

a gate electrode formed on the gate dielectric layer;

a pair of source/drain regions on opposite sides of the gate electrode, the pair of source/drain regions comprising a doped semiconductor film directly beneath the gate electrode, wherein the semiconductor film has a bandgap of less than 0.75 eV; and

a pair of non-alloyed contacts on the doped semiconductor film.

5. The transistor of claim 4 wherein the non-alloyed contacts comprise a bi-layer of titanium/gold.

6. The transistor of claim 4 wherein the semiconductor film is selected from the group consisting of indium antimonide (InSb), indium arsenide (InAs), indium gallium arsenide (In_1-xGa_xAs(x>

50%)) and indium phosphide (InP).

10. The transistor of claim 4 wherein the semiconductor film is indium phosphide (InP).

14. The transistor of claim 4 wherein the semiconductor film is doped to an n type conductivity.

15. The transistor of claim 14 wherein the indium phosphide (InP) film is doped to the n type conductivity with a dopant selected from the group consisting of tellurium (Te), silicon (Si) and sulfur (S).

17. The transistor of claim 4 wherein the semiconductor film is doped to a p type conductivity.

18. The transistor of claim 17 wherein the semiconductor film is doped to the p type conductivity with a dopant selected from the group consisting of carbon (C), cadmium (Cd), zinc (Zn) and chromium (Cr).

8. A transistor comprising:

a gate dielectric layer formed on a silicon-on-insulator (SOI) substrate;

a gate electrode formed on the gate dielectric layer; and

a pair of source/drain regions on opposite sides of the gate electrode, the pair of source/drain regions comprising a doped semiconductor film directly beneath the gate electrode, wherein the semiconductor film has a bandgap of less than 0.75 eV;

wherein the SOI substrate comprises a silicon body having a top surface opposite a bottom surface formed on an insulating layer, and wherein the gate dielectric layer is formed on the top surface and sidewalls of the silicon body and the gate electrode is formed on the gate dielectric layer on the top surface of the silicon body and adjacent to the gate dielectric layer on the sidewalls of the silicon body.

9. A transistor comprising:

a gate dielectric layer formed on a silicon-on-insulator (SOI) substrate;

a gate electrode formed on the gate dielectric layer; and

a pair of source/drain regions on opposite sides of the gate electrode, the pair of source/drain regions comprising a doped semiconductor film directly beneath the gate electrode, wherein the semiconductor film has a bandgap of less than 0.75 eV and an electron mobility greater than 10,000 cm²V<sup>−

1</sup>s<sup>−

1</sup>.

16. The transistor of claim 9 wherein the SOI substrate comprises a silicon body having a top surface opposite a bottom surface formed on an insulating layer, and wherein the gate dielectric layer is formed on the top surface and sidewalls of the silicon body and the gate electrode is formed on the gate dielectric layer on the top surface of the silicon body and adjacent to the gate dielectric layer on the sidewalls of the silicon body.