No-lead IC packages having integrated heat spreader for electromagnetic interference (EMI) shielding and thermal enhancement
First Claim
1. An integrated circuit (IC) device package, comprising:
- an IC die having bond pads;
an encasing structure that substantially encloses the IC die, comprising;
a leadframe, including;
a die attach pad having a substantially planar central portion with opposing first and second surfaces, wherein the first surface of the central portion of the die attach pad has the IC die mounted on,a plurality of tie bars, each tie bar being coupled to the die attach pad, wherein a. tie bar of the plurality of tie bars comprises at least one receptacle, anda plurality of leads emanating outward from the IC die, each lead being coupled to a bond pad of the bond pads, wherein a tie bar of the plurality of tie bars is coupled to at least two leads of the plurality of leads; and
a cap having a cavity and a planar rim surrounding the cavity, such that the cavity faces the IC die, wherein the cap is coupled to the leadframe, wherein the cap comprises at least one tab protruding from the planar rim, and wherein the at least one tab mates with the at least one receptacle; and
a molding material that substantially encapsulates the IC die and at least partially fills the cavity.
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Accused Products
Abstract
Methods and apparatus for improved thermal performance and electromagnetic interference (EMI) shielding in integrated circuit (IC) packages are described. A die-up or die-down package includes an IC die, a die attach pad, a heat spreader cap coupled to the die attach pad defining a cavity, and one or more peripheral rows of leads surrounding the die attach pad. The leads do not protrude substantially from the footprint of the encasing structure. The die attach pad and the heat spreader cap defines an encasing structure that substantially encloses the IC die, and shields EMI emanating from and radiating towards the IC die. The encasing structure also dissipates heat generated by the IC die during operation.
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Citations
49 Claims
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1. An integrated circuit (IC) device package, comprising:
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an IC die having bond pads; an encasing structure that substantially encloses the IC die, comprising; a leadframe, including; a die attach pad having a substantially planar central portion with opposing first and second surfaces, wherein the first surface of the central portion of the die attach pad has the IC die mounted on, a plurality of tie bars, each tie bar being coupled to the die attach pad, wherein a. tie bar of the plurality of tie bars comprises at least one receptacle, and a plurality of leads emanating outward from the IC die, each lead being coupled to a bond pad of the bond pads, wherein a tie bar of the plurality of tie bars is coupled to at least two leads of the plurality of leads; and a cap having a cavity and a planar rim surrounding the cavity, such that the cavity faces the IC die, wherein the cap is coupled to the leadframe, wherein the cap comprises at least one tab protruding from the planar rim, and wherein the at least one tab mates with the at least one receptacle; and a molding material that substantially encapsulates the IC die and at least partially fills the cavity. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 15, 17, 18, 19, 20, 21, 22, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49)
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14. An integrated circuit (IC) device package, comprising:
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an IC die having bond pads; an encasing structure that substantially encloses the IC die, comprising; a die attach pad having a substantially planar central portion with opposing first and second surfaces, and a plurality of tie bars coupled to and extending from the central portion, wherein the first surface of the central portion of the die attach pad has the IC die mounted on thereon, and a cap having a cavity and a planar rim surrounding the cavity, such that the cavity faces the IC die when the rim is attached to the die attach pad, thereby enclosing the IC die; a plurality of leads having lead fingers for wire bonding arranged in at least one peripheral row surrounding the die attach pad; and a molding material that substantially encapsulates the IC die and at least partially fills the cavity, wherein at least one of the plurality of tie bars is wider relative to others of the plurality of tie bars.
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16. An integrated circuit (IC) device package, comprising:
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an IC die having bond pads; an encasing structure that substantially encloses the IC die, comprising; a die attach pad having a substantially planar central portion with opposing first and second surfaces, and a plurality of tie bars coupled to and extending from the central portion, wherein the first surface of the central portion of the die attach pad has the IC die mounted on thereon, and a cap having a cavity and a planar rim surrounding the cavity, such that the cavity faces the IC die when the rim is attached to the die attach pad, thereby enclosing the IC die; a plurality of leads having lead fingers for wire bonding arranged in at least one peripheral row surrounding the die attach pad; and a molding material that substantially encapsulates the IC die and at least partially fills the cavity, wherein the cap is in electrical and thermal contact with at least one tie bar.
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23. An integrated circuit (IC) device package, comprising:
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an IC die having bond pads; an encasing structure that substantially encloses the IC die, comprising; a die attach pad having a substantially planar central portion with opposing first and second surfaces, and a plurality of tie bars coupled to and extending from the central portion, wherein the first surface of the central portion of the die attach pad has the IC die mounted on, and a cap having a cavity and a planar rim surrounding the cavity, such that the cavity faces the IC die when the rim is attached to the die attach pad, thereby enclosing the IC die; a plurality of leads having lead fingers for wire bonding arranged in at least one peripheral row surrounding the die attach pad; and a molding material that substantially encapsulates the IC die and at least partially fills the cavity, Wherein the cap is coupled to a power potential.
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Specification