Reconfigurable IC that has sections running at different reconfiguration rates

• US 8,183,882 B2
• Filed: 12/21/2009
• Issued: 05/22/2012
• Est. Priority Date: 11/08/2004
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Tabula Incorporated
• Inventors: Teig, Steven, Schmit, Herman, Redgrave, Jason
• Primary Examiner(s): Tan, Vibol
• Application Number:
  US12/644,008
• Publication Number:
  US 20100194429A1
• Time in Patent Office: 883 Days
• Field of Search: 326 38- 41, 326/47, 713/300, 713/322, 713/375, 713/400, 713/500
• US Class Current: 326/38
• CPC Class Codes: H03K 19/17756 for partial configuration or partial reconfiguration
• CPC Class Codes: H03K 19/17758 for speeding up configuration or reconfiguration

Abstract

Some embodiments provide a reconfigurable IC that includes several sections. Each section includes several configurable circuits, each of which configurably performs a set of operations. Each section stores multiple configuration data sets for each configurable circuit. Each configuration data set for a particular configurable circuit specifies the operation that the particular configurable circuit has to perform from the circuit'"'"'s set of operations, where the configurable circuits of at least two different sections change configuration data sets at two different reconfiguration rates.

Claims

1. An integrated circuit (IC) comprising:

first and second groups of reconfigurable circuits,each reconfigurable circuit of the first group for performing a plurality of operations at a first reconfiguration rate,

each reconfigurable circuit of the second group for performing a plurality of operations at a second reconfiguration, wherein the first reconfiguration rate is different than the second reconfiguration rate, wherein each reconfigurable circuit has a plurality of sets of storage elements that store a plurality of configuration data sets; and

for each reconfigurable circuit, a set of configuration retrieval circuits for iteratively reading, in a looping manner, different sets of storage elements of the reconfigurable circuit in order to retrieve configuration data sets for reconfiguring the reconfigurable circuit.

2. The IC of claim 1 wherein a particular configuration retrieval circuit couples its input to different sets of storage elements storing a plurality of configuration data sets in order to iteratively select a configuration data set in each of a plurality of periods to supply to the reconfigurable circuit.

3. The IC of claim 1, wherein the first group of reconfigurable circuits implements an input and output interface of the IC.

4. The IC of claim 3, wherein the second group of reconfigurable circuits implements a user design.

5. The IC of claim 1 further comprising a third group of reconfigurable circuits for performing a set of operations at a third reconfiguration rate, wherein the third reconfiguration rate is different than the first and second reconfiguration rates.

6. An integrated circuit (IC) comprising:

a plurality of sections;

each section including a plurality of reconfigurable logic circuits and a plurality of reconfigurable logic circuits and a plurality of reconfigurable routing circuits;

each reconfigurable logic circuit for reconfigurably performing a set of operations;

each reconfigurable routing circuit for reconfigurably providing different connection schemes, said reconfigurable routing circuits for reconfigurably connecting the reconfigurable logic circuits;

each section storing a plurality of configuration data sets for each reconfigurable circuit;

each configuration data set for a particular reconfigurable logic circuit specifying an operation that the particular reconfigurable logic circuit has to perform from the circuit'"'"'s set of operations;

each configuration data set for a particular reconfiguration routing circuit specifying a connection scheme for the particular reconfigurable routing circuit to provide;

wherein the reconfigurable circuits of at least two different sections change configuration data sets at two different reconfiguration rates.

7. The IC of claim 6, wherein the two different sections are first and second sections, wherein the two different reconfiguration rates are defined by first and second clocks, wherein the first clock defines the reconfiguration rate in the first section while the second clock defines the reconfiguration rate in the second section, wherein the first and second clocks are clocks globally distributed to the reconfigurable circuits of the reconfigurable IC.

8. The IC of claim 7, wherein the first and second clocks define first and second clock domains within the IC.

9. The IC of claim 7 further comprising:

for each particular reconfigurable circuit, configuration data supplying circuitry for supplying configuration data sets to the particular reconfigurable circuit;

in the first section, at least a first local signal generator for generating signals based on the first clock to control the configuration data supplying circuitry in the first section; and

in the second section, at least a second local signal generator for generating signals based on the second clock to control the configuration data supplying circuitry in the second section.

10. The IC of claim 6, wherein specifying the connection scheme comprises specifying an interconnect operation for the particular reconfigurable routing circuit to perform within the reconfigurable routing circuit'"'"'s set of interconnect operations.

11. The IC of claim 6, wherein the reconfigurably connecting the plurality of reconfigurable logic circuits comprises configurably routing signals between the plurality of reconfigurable logic circuits.

12. The IC of claim 6, wherein the plurality of reconfigurable routing circuits include reconfigurable input-select interconnect circuits for reconfigurably selecting signals that are input signals to the reconfigurable logic circuits. each reconfigurable routing circuit for reconfigurably providing different connection schemes, said reconfigurable routing circuits for reconfigurably connecting the reconfigurable logic circuits.

13. A method for operating an integrated circuit (IC) with a plurality of reconfigurable circuits, the method comprising:

in different sections of the IC, reconfiguring the reconfigurable circuits at different reconfiguration rates;

the reconfiguring comprising;

for a first reconfigurable circuit in a first section,

repeatedly retrieving a first sequence of configuration data sets from a first sequence of storage element sets, and

supplying repeatedly the retrieved configuration data sets to the first reconfigurable circuit to perform a first sequence of operations repeatedly; and

for a second reconfigurable circuit in a second section,

repeatedly retrieving a second sequence of configuration data sets from a second sequence of storage element sets, and

supplying repeatedly the retrieved configuration data sets to the second reconfigurable circuit to perform a second sequence of operations repeatedly,

wherein the rate of retrieval for the first reconfigurable circuit is different from the rate of retrieval for the second reconfigurable circuit.

14. The method of claim 13, wherein the first section of the IC stores N configuration data sets for each of a set of reconfigurable circuits in the first section, while the second section of the IC stores M configuration data sets for each of a set of reconfigurable circuits in the second section, wherein N and M are different integers.

15. The method of claim 13, wherein each particular reconfigurable circuit is coupled to a configuration data supplying circuit that supplies the particular reconfigurable circuit'"'"'s configuration data sets.

16. The method of claim 15, wherein a first configurable data supplying circuitry in the first section is controlled differently than a second configurable data supplying circuitry in the second section.

17. The method of claim 14, wherein a first configurable data supplying circuitry iterates through a smaller sub-set of configuration data sets for the first reconfigurable circuit than configuration data sets iterated through by a second configurable data supplying circuitry for the second reconfigurable circuit.

18. The method of claim 14, wherein first and second sections have storage capacity to store a same number of configuration data sets for each reconfigurable circuit in the two sections, but a reconfigurable circuit in the first section iterates through a smaller sub-set of the configuration data sets than a reconfigurable circuit in the second section.

19. The method of claim 13, wherein the reconfigurable circuits include reconfigurable logic circuits each for reconfigurably performing a set of functions, wherein a configuration data set for a reconfigurable logic circuit specifies a function for the reconfigurable logic circuit to perform within the reconfigurable logic circuit'"'"'s set of functions.

20. The method of claim 19, wherein the reconfigurable circuits further include reconfigurable interconnect circuits each for reconfigurably performing a set of interconnect operations, wherein a configuration data set for a reconfigurable interconnect circuit specifies an interconnect operation for the reconfigurable interconnect circuit to perform within the reconfigurable interconnect circuit'"'"'s set of interconnect operations.