Integrated circuits including a charge pump circuit and operating methods thereof

• US 8,183,913 B2
• Filed: 02/17/2010
• Issued: 05/22/2012
• Est. Priority Date: 02/17/2010
• Status: Expired

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Swei, Steven, Lin, Chih-Chang, Yang, Tien-Chun, Chern, Chan-Hong, Huang, Ming-Chieh
• Primary Examiner(s): Donovan, Lincoln
• Assistant Examiner(s): Cole, Brandon S
• Application Number:
  US12/706,886
• Publication Number:
  US 20110199152A1
• Time in Patent Office: 825 Days
• Field of Search: 327/141, 327144-163, 327535-537, 331/1.A, 331 15- 17, 375373-376, 363/59, 363/60
• US Class Current: 327/537
• CPC Class Codes: G05F 1/10 Regulating voltage or current G05F1/02 takes precedence; for electric railways B60M3/02
• CPC Class Codes: G05F 3/02 Regulating voltage or current
• CPC Class Codes: H03L 7/0895 Details of the current generators H03L7/0893 takes precedence
• CPC Class Codes: H03L 7/0896 the current generators being controlled by differential up-down pulses
• CPC Class Codes: H03L 7/0898 the source or sink current values being variable H03L7/0896 takes precedence

Abstract

An integrated circuit includes a first current source. A second current source is electrically coupled with the first current source via a conductive line. A switch circuit is coupled between the first current source and the second current source. A first circuit is coupled between a first node and a second node. The first node is disposed between the first current source and the switch circuit. The second node is coupled with the first current source. The first circuit is configured for substantially equalizing voltages on the first node and the second node. A second circuit is coupled between a third node and a fourth node. The third node is disposed between the second current source and the switch circuit. The fourth node is disposed coupled with the second current source. The second circuit is configured for substantially equalizing voltages on the third node and the fourth node.

Claims

1. An integrated circuit comprising:

a first current source;

a second current source electrically coupled with the first current source via a conductive line;

a switch circuit coupled between the first current source and the second current source;

a first circuit coupled between a first node and a second node, the first node being disposed between the first current source and the switch circuit, the second node being coupled with the first current source, wherein the first circuit is configured for substantially equalizing voltages on the first node and the second node;

a second circuit coupled between a third node and a fourth node, the third node being disposed between the second current source and the switch circuit, the fourth node being coupled with the second current source, wherein the second circuit is configured for substantially equalizing voltages on the third node and the fourth node;

a third current source;

a comparator coupled between the second current source and the third current source;

a controller coupled with an output end of the comparator; and

an adjustable resistance circuit coupled with the controller, the adjustable resistance circuit being disposed between the first circuit and the second circuit.

2. The integrated circuit of claim 1, wherein

the first current source includes a first transistor and a second transistor;

the second current source includes a third transistor and a fourth transistor;

the first circuit is disposed between drains of the first and second transistors, wherein the first circuit is configured for substantially equalizing voltages on the drains of the first and second transistors; and

the second circuit is disposed between drains of the third and fourth transistors, wherein the second circuit is configured for substantially equalizing voltages on the drains of the third and fourth transistors.

3. The integrated circuit of claim 2, wherein the first circuit comprises

a first amplifier coupled between the drains of the first and second transistors;

and

a fifth transistor having a gate coupled with an output end of the first amplifier.

4. The integrated circuit of claim 3, wherein the second circuit comprises:

a second amplifier coupled between the drains of the third and fourth transistors; and

a sixth transistor having a gate coupled with an output end of the second amplifier.

5. The integrated circuit of claim 4, wherein each of the first and second amplifiers has a gain of about 60 dB or more.

6. The integrated circuit of claim 1, wherein the comparator is configured to compare a first current from the second current source and a second current from the third current source to output a signal for triggering the controller to adjust a resistance of the adjustable resistance circuit.

7. The integrated circuit of claim 1, wherein the controller includes a counter, the adjustable resistance circuit includes a series of resistors and a series of switches, and each of the switches is disposed in parallel with a corresponding one of the resistors, wherein the counter is configured to turn on or off at least one of the switches to adjust a resistance of the adjustable resistance circuit.

8. An integrated circuit comprising:

a first current source;

a second current source;

a switch circuit coupled between the first current source and the second current source, wherein a first node is between the first current source and the switch circuit, and a second node is between the second current source and the switch circuit;

a first transistor coupled with the first current, wherein a third node is disposed between the first transistor and the first current source;

a first amplifier coupled between the first node and the third node;

a second transistor coupled with the second current source, wherein a fourth node is disposed between the second transistor and the second current source;

a second amplifier coupled between the second node and the fourth node

a third current source;

a comparator coupled between the second current source and the third current source;

a controller coupled with an output end of the comparator; and

an adjustable resistance circuit coupled with the controller, the adjustable resistance circuit being disposed between the first transistor and the second transistor.

9. The integrated circuit of claim 8, wherein each of the first and second amplifiers has a gain of about 60 dB or more.

10. The integrated circuit of claim 8, wherein the comparator is configured to compare a first current from the second current source and a second current from the third current source to output a signal for triggering the controller to adjust a resistance of the adjustable resistance circuit.

11. The integrated circuit of claim 10, wherein the controller includes a counter, the adjustable resistance circuit includes a series of resistors and a series of switches, and each of the switches is disposed in parallel with a corresponding one of the resistors, wherein the counter is configured to turn on or off at least one of the switches to adjust a resistance of the adjustable resistance circuit.

12. A method of operating a charge pump circuit of a phase-locked system, the method comprising:

substantially equalizing voltages on a first node and a second node, wherein the first node is disposed between a first current source and a switch circuit of the charge pump circuit, and the second node is coupled with the first current source;

substantially equalizing voltages on a third node and a fourth node, wherein the third node is disposed between the switch circuit and a second current source of the charge pump circuit, and the fourth node is coupled with the second current source; and

adjusting a resistance of an adjustable resistance circuit disposed between the first node and the third node so as to adjust a charge pump current flowing through the first current source and the second current source.

13. The method of claim 12, wherein substantially equalizing voltages on the first node and the second node comprises:

detecting the voltages on the first node and the second node; and

adjusting the voltage on the second node so as to substantially equalize the voltages on the first node and the second node.

14. The method of claim 13, wherein detecting the voltages on the first node and the second node comprises detecting the voltages on drains of a first transistor and a second transistor of the first current source.

15. The method of claim 12, wherein substantially equalizing voltages on the third node and the fourth node comprises:

detecting the voltages on the third node and the fourth node; and

adjusting the voltage on the fourth node so as to substantially equalize the voltages on the third node and the fourth node.

16. The method of claim 15, wherein detecting the voltages on the third node and the fourth node comprises detecting the voltages on drains of a third transistor and a fourth transistor of the second current source.

17. The method of claim 12, wherein adjusting the resistance of the adjustable resistance circuit comprises:

comparing the charge pump current with a predetermined current so as to generate an output signal; and

responding to the output signal, adjusting the resistance of the adjustable resistance circuit such that the charge pump current is substantially equal to the predetermined current.