Integrated high frequency BALUN and inductors

• US 8,183,970 B2
• Filed: 10/04/2010
• Issued: 05/22/2012
• Est. Priority Date: 08/31/2004
• Status: Active Grant

• Current Assignee: Theta IP, LLC
• Original Assignee: Theta Microelectronics, Inc.
• Inventors: Papananos, Yannis
• Primary Examiner(s): Nguyen, Tuyen
• Application Number:
  US12/897,446
• Publication Number:
  US 20110018672A1
• Time in Patent Office: 596 Days
• Field of Search: 336/200, 336/232, 257/531, 296/021
• US Class Current: 336/200
• CPC Class Codes: H01F 17/0013 with stacked layers
• CPC Class Codes: H01F 2017/0086 on semiconductor substrate inductors for integrated circuits H01L28/10
• CPC Class Codes: H01F 2027/2809 on stacked layers
• CPC Class Codes: H01F 27/2804 Printed windings
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H03H 2001/0064 comprising semiconductor material
• CPC Class Codes: H03H 7/42 Networks for transforming balanced signals into unbalanced signals and vice versa, e.g. baluns
• CPC Class Codes: Y10T 29/4902 Electromagnet, transformer or inductor
• CPC Class Codes: Y10T 29/49071 by winding or coiling
• CPC Class Codes: Y10T 29/49073 by assembling coil and core

Abstract

Integrated high frequency balanced-to-unbalanced transformers and inductors suitable for operation in high frequencies, such as radio frequencies. Embodiments disclosed give consideration to issues related to the layout of the top and bottom inductors for the minimization of capacitive effects between layers and methods of manufacturing thereof. A displacement between the conductive paths of the top inductor and the bottom inductor is shown that provides for superior performance over prior art solutions.

Claims

1. A method for manufacturing an on-chip inductor using standard manufacturing processes, the method comprising:

forming a first inductor from a first clockwise winding conductive path in a first metal layer and a first counterclockwise winding conducting path in the first metal layer, the first clockwise winding and the first counterclockwise winding conductive path being essentially symmetrical, each forming from an internal edge toward an external edge of the respective conducting path, the external edges of the first clockwise winding conductive path and the first counterclockwise winding of the conductive path being connected;

forming a first insulating layer using an insulating material;

forming shunts in a second metal layer to ensure the continuity of the first clockwise winding and the first counterclockwise winding at crossover points;

forming a second insulating layer using an insulating material;

forming a second inductor from a second clockwise winding conductive path in a third metal layer and a second counterclockwise winding in the third metal layer, the second clockwise winding and the first counterclockwise winding being essentially symmetrical, the second clockwise winding and the second counterclockwise winding being formed at a displacement from the first clockwise winding and the first counterclockwise winding, each forming from an external edge towards an internal edge of the respective conducting path;

forming a third insulating layer using an insulating material;

forming shunts in a forth metal layer to ensure the continuity of the second clockwise winding and the second counterclockwise winding at crossover points;

forming shunts to connect the internal edge of the first clockwise winding conductive path with the internal edge of the second clockwise winding conductive path; and

,

forming shunts to connect the internal edge of the first counterclockwise winding conductive path with the internal edge of the second counterclockwise winding conductive path;

the shunts connecting between the first inductor and the second inductor being formed such that the current flow through the inductor is always toward the same direction so the mutual inductance of the inductor is developed in favor of the overall spiral inductance.

2. The method of claim 1 further comprising:

setting the displacement to essentially result in an overlap between the conducting paths of the first inductor and the conducting paths of the second inductor not to exceed fifty percent of a width of at least one of the conducting paths.

3. The method of claim 1 further comprising:

setting the displacement to result in essentially no overlap between the conducting paths of the first inductor and the conductive paths of the second inductor.

4. The method of claim 1 further comprising:

forming a center tap of the inductor at the connection point of the external edges of the first clockwise winding conductive path and the first counterclockwise winding conductive path.

5. The method of claim 1 further comprising:

forming a first port and a second port to the inductor, the first port and the second port connected to an external edge of the second inductor.

6. The method of claim 1 further comprising:

forming at least one of the first metal and the third metal from two layers of metal connected in parallel by a plurality of shunts.

7. A device formed in an integrated circuit (IC) comprising:

a first winding conductive path formed in a first metal layer of the IC, the first winding conductive path being at least a portion of a spiral; and

a second winding conductive path formed in a second metal layer of the IC and essentially insulated by at least an insulating layer formed over the first metal layer, the second winding conductive path being at least a portion of a spiral;

the conductive path of the first winding and the conductive path of the second winding formed to be horizontally displaced from each other to reduce capacitive coupling between the first winding and the second winding;

wherein the displacement provides an overlap between the first winding conductive path and the second winding conductive path that does not to exceed fifty percent of at least one of the width of the first winding conductive path and the second winding conductive path.

8. The device of claim 7, wherein said first winding and said second winding form at least a portion of a balanced-to-unbalanced (BALUN) transformer.

9. The device of claim 7, wherein said first winding and said second winding form at least a portion of an inductor.

10. The device of claim 7, further comprising shunts to create a conductive path at intersection points of any one of:

first winding, second winding.

11. The device of claim 7, wherein the displacement provides for no overlap between the first winding conductive path and the second winding conductive path.